EP0617518A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Variable length codeword packer

Assignee: Arris Technology Inc

•

Filing: 1994-03-23

•

Granted: —

•

Expires: 2014-03-23

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A variable length codeword packer (Fig. 3) communicates codeword data in successive m-bit bytes. A binary sum is accumulated (86) indicative of a total number of codeword bits received over time. A byte pointer (90) is derived from at least one most significant bit of the binary sum. A bit pointer (92) is derived from a plurality of least significant bits of the binary sum. A first data storage array (20) has a plurality of m-bit first storage bytes and is responsive to the byte pointer for storing received codeword data in the first storage bytes. A second data storage array (22) has a plurality of m-bit second storage bytes and is responsive to the byte and bit pointers for filling the second storage bytes with codeword data from the first data storage array (20). m-bit bytes of codeword data (25) are output from each filled second storage byte to provide successive m-bit bytes of codeword data. The use of a multistage approach in packing variable length codewords substantially reduces the complexity as compared to single stage designs. <IMAGE>

Inventors

👤 Henry Derovanessian
👤 Vincent Liu

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-04 12:29

CPC Classifications

H; H03; H03M; H03M7/00; H03M7/30; H03M7/40

Claims Analysis

Total Claims: 7

Claim 1

Independent Claim 244 words

A variable length codeword packer for use in communicating codeword data in successive m-bit bytes comprising: means for accumulating a binary sum indicative of a total number of codeword bits received over time; means for deriving a byte pointer from at least one most significant bit of said binary sum; means for deriving a bit pointer from a plurality of least significant bits of said binary sum; a first data storage array having a plurality of m-bit first storage bytes and responsive to said byte pointer for storing codeword data in said first storage bytes; a second data storage array having a plurality of m-bit second storage bytes and responsive to said byte and bit pointers for filling said second storage bytes with codeword data from said first data storage array; and means for outputting an m-bit byte of codeword data from each filled second storage byte to provide successive m-bit bytes of codeword data; wherein: incoming variable length codewords are successively stored in said first data storage array, each codeword commencing at the beginning of a first storage byte identified by said byte pointer based on the binary sum of preceding codeword bit lengths, and each of the variable length codewords stored in said first data storage array is transferred to said second data storage array commencing at a location within a second storage byte identified by said byte pointer and bit pointer based on the binary sum of preceding codeword bit lengths.

Claim 2

Dependent Claim 45 words

A variable length codeword packer in accordance with claim 1 wherein said incoming codewords are grouped in sets containing a plurality of codewords, said codeword packer further comprising: means for resetting said accumulating means to zero at the beginning of each new set of codewords.

Claim 3

Dependent Claim 43 words

A variable length codeword packer in accordance with claim 1 or 2 wherein said codewords have a maximum length of n bits, each of said first and second data storage arrays comprise k storage bytes, and each storage byte contains m cells, where

Claim 4

Dependent Claim 78 words

A variable length codeword packer in accordance with one of the preceding claims wherein said accumulating means comprise a q-bit accumulator with the p least significant bits thereof forming said bit pointer and the remaining (q-p) most significant bits forming said byte pointer, where p is the number of bits required to identify any one of m cells in a storage byte and (q-p) is the number of bits required to identify any one of k storage bytes.

Claim 5

Dependent Claim 91 words

A variable length codeword packer in accordance with one of the preceding claims further comprising clock means for: clocking said codeword data into said first data storage array one codeword at a time, clocking said byte pointer into said first data storage array when a corresponding codeword is clocked therein, clocking said codeword data from said first data storage array into said second data storage array one codeword at a time, and clocking said byte and bit pointers into said second data storage array when a corresponding codeword is clocked therein.

Claim 6

Dependent Claim 61 words

A variable length codeword packer in accordance with claim 5 wherein the codeword data is clocked into said second data storage array one clock cycle after it is clocked into said first data storage array, said codeword packer further comprising: means for delaying the clocking of said byte and bit pointers into said second data storage array by one clock cycle.

Claim 7

Dependent Claim 38 words

A variable length codeword packer in accordance with one of the preceding claims wherein said outputting means are responsive to an incrementing of said byte pointer for outputting data from a second storage byte that has been filled.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)