Silicon on insulator semiconductor device and its fabrication method

Claim 2

A semiconductor device according to claim 1, wherein in said first, second and third semiconductor regions reside on an insulating substrate, and said first, second and third semiconductor regions may be disposed to be in contact with one another in the order of said second, first and third semiconductor regions, and with said insulating substrate to have a Silicon on Insulator (SOI) structure.

Claim 3

A semiconductor device according to claim 1, wherein said first, second and third semiconductor regions reside on a bulk semiconductor, and semiconductors in said first, second and third semiconductor regions may be disposed to be in contact with one another in the order of said second, first and third semiconductor regions, and with said insulating substrate to have a structure.

Claim 4

A semiconductor device according to any one of claims 1 to 3, wherein the work function of said control electrode material, the film thickness of said insulating layer, and the impurity concentration of said semiconductor region of the first conduction type are set so that said first semiconductor region in contact with said insulating layer may be in weak inversion state.

Claim 5

A semiconductor device according to claims 1 to 4, wherein said control electrode is a gate electrode, said first semiconductor region is a channel region directly below the gate electrode, and said second and third semiconductor regions are a source region and a drain region, respectively, to constitute a MOS transistor.

Claim 6

A semiconductor device according to claims 1 to 5, wherein said first semiconductor region in contact with said insulating layer is in weak inversion state, and a depletion layer with a MOS structure reaches said insulating substrate.

Claim 7

A semiconductor device according to claim 5 or 6, wherein the work function of said control electrode material, the film thickness of said insulating layer, and the impurity concentration and film thickness of said semiconductor region of the first conduction type are set so that said first semiconductor region in contact with said insulating layer may be in weak inversion state.

Claim 8

A semiconductor device according to any one of claims 1 to 5, wherein said first semiconductor region is a base region, and said second and third semiconductor regions are an emitter region and a collector region, respectively, to constitute a bipolar transistor.

Claim 9

A semiconductor device according to claim 8, wherein the distance from emitter junction of said base region to collector junction is equal to or less than 0.3 µm.

Claim 10

A semiconductor device according to claim 1, wherein a base region of said first semiconductor region is formed by diffusion of impurities from the substrate surface, and said control electrode is formed via an insulating film on the side of said base region to constitute a bipolar transistor.

Claim 11

A semiconductor device according to claim 10, wherein the impurity concentration profile in said base region is smaller from emitter junction to collector junction.

Claim 12

A semiconductor device according to claim 10 or 11, wherein two or more emitter regions serving as said second semiconductor region are formed.

Claim 13

A semiconductor device according to any one of claims 10 to 12, wherein a thin oxide film is provided between the emitter region serving as said second semiconductor region and the emitter electrode, the conduction between said emitter region and said emitter electrode being through the use of tunnel current.

Claim 14

A semiconductor device according to any one of claims 10 to 13, wherein said semiconductor device is made on an insulator to constitute an SOI (Silicon on Insulator).

Claim 15

A semiconductor device according to any one of claims 10 to 14, wherein the emitter region serving as said second semiconductor region is constituted from a semiconductor having a larger forbidden band width than the semiconductor constituting said base region.

Claim 16

A semiconductor device according to claim 15, wherein said semiconductor having larger forbidden band width is made of microcrystalline or amorphous semiconductor.

Claim 17

A semiconductor device according to claim 15, wherein said semiconductor having large forbidden band width is made of SiC.

Claim 18

A fabrication method for a semiconductor device wherein an emitter region, a base region and a collector region are laterally formed on an SOI substrate having a semiconductor region on the surface of an insulating layer or insulator, and comprising an electrode for controlling the conduction type of the base region via an insulating film, characterized by including the following processes (A) to (E) which are performed in sequence: (A) a process of forming a first insulating film region and a second insulating film region having a greater thickness than that of said first insulating film region on said semiconductor layer of the first conduction type provided on the surface of said insulating layer or said insulator; (B) a process of introducing and activating impurities of the second conduction type into said second semiconductor region below said first insulating film region with said second insulating film region as a mask; (C) a process of depositing a conduction film on said first and second insulating film regions and forming a control electrode by anisotropic etching to leave behind at least a side wall conduction film deposited in a stepped side wall portion between said first insulating film region and said second insulating film region to be directly above the base region; (D) a process of making said emitter region and said collector region by introducing and activating impurities of the first conduction type with said control electrode and said second insulating film region as a mask; and (E) a process of electrically connecting said control electrode with a lead-out electrode of said base region.

Claim 19

A fabrication method of semiconductor device according to claim 18, further comprising a process of implanting C ions into the emitter region in performing said process (D) to constitute the emitter region of SiC.

Claim 20

A fabrication method of semiconductor device according to claim 18, further comprising a process of implanting Si ions into said emitter region in performing said process (D) to constitute said emitter region of microcrystalline semiconductor or amorphous semiconductor.

Claim 21

A fabrication method of semiconductor device wherein an emitter region, a base region, and a collector region are vertically formed, and the conduction type of said base region is controlled via a control electrode, characterized by including at least the following processes (A) to (E) which are performed in sequence: (A) a process of implanting impurity ions from the surface to make on a semiconductor substrate of the first conduction type, a well region of the second conduction type opposite to that of said semiconductor substrate, and conducting heat treatment; (B) a process of making epitaxial growth to deposit a region with small impurity concentration of the second conduction type equal to that of said well region on said well region (the region made through this process is hereinafter abbreviated as an epitaxial region); (C) a process of implanting impurity ions of the second conduction type into a part of said epitaxial region to make said emitter region a high concentration impurity region; (D) a process of removing selectively said epitaxial region; (E) a process of depositing an insulating region on said epitaxial region; (F) a process of depositing a low resistive region on said insulating region and removing it with only the portion serving as a control electrode left behind; (G) a process of depositing a new insulating region to cover said control electrode; (H) a process of making said base region by implanting impurity ions of the first conduction type into said epitaxial region; and (J) a process of making said emitter region by implanting impurity ions of the second conduction type into said epitaxial region.

Claim 22

A fabrication method of semiconductor device according to claim 21, further comprising a process of implanting C ions in implanting impurity ions into said epitaxial region in the (J) process to constitute said emitter region of SiC to have a greater forbidden band width.

Claim 23

A fabrication method of semiconductor device according to claim 21, further comprising a process of implanting Si ions in implanting impurity ions into said epitaxial region in the (J) process to constitute said emitter region of microcrystalline or amorphous Si to have a greater forbidden band width.

Claim 24

A fabrication method of semiconductor device according to any one of claims 21 to 23, further comprising a process (K) of depositing said insulating film on said epitaxial region which becomes an emitter region to render the current from emitter electrode to emitter region passing through the insulating film only a tunnel current after the (J) process.

Claim 25

A fabrication method of semiconductor device according to any one of claims 21 to 24, wherein a plurality of emitter regions are made by implanting impurity ions of the second conduction type into the plurality of regions in the process (C).