Semiconductor device provided with isolation region

Claim 2

A semiconductor device provided with an isolation region between circuit elements, comprising: a substrate having an insulation layer on a surface thereof; a monocrystalline semiconductor layer disposed on said substrate through said insulation layer, said monocrystalline semiconductor layer being divided into a plurality of islands for circuit element formation by a trench extending to said insulation layer from a surface of said monocrystalline semiconductor layer, and said trench being provided around each of said plurality of islands for circuit element formation; a lateral insulation layer for burying said trench therein; an island for capacitive coupling prevention having one conductivity type and formed by said monocrystalline semiconductor layer, said island for capacitive coupling prevention being disposed between said plurality of islands for circuit element formation and independent from said plurality of islands for circuit element formation by said trench; means for applying an electric potential to fix said island for capacitive coupling prevention in an electric potential of constant; and a semiconductor layer of one conductive type formed at a lower surface of said monocrystalline semiconductor layer constructing said island for capacitive coupling prevention and having a concentration higher than said monocrystalline semiconductor layer of said island for capacitive coupling prevention.

Claim 3

A semiconductor device as claimed in Claim 2, wherein said islands for circuit element formation have an N⁺ emitter region, a P⁺ base region and an N⁻ collector region, a P⁺ diffusion region for extracting excessive carriers being formed in said N⁻ collector region.

Claim 4

A semiconductor device as claimed in Claim 3, wherein an oxide film is formed on a surface of said semiconductor substrate, and a plate electrode is disposed on said oxide film between said P⁺ base region and said P⁺ diffusion region for extracting excessive carriers.

Claim 5

A semiconductor device as claimed in Claim 4, wherein a region of one conductivity type with high concentration is formed at a surface of said island for capacitive coupling prevention, and said region and said plate electrode are electrically connected, an electric potential of said island for capacitive coupling prevention being maintained in a high level.

Claim 6

In a semiconductor device in which plural circuit elements are formed on a monocrystalline semiconductor substrate provided on an insulation film, the semiconductor device is characterized by provision of: islands for circuit element formation formed of a material of the monocrystalline semiconductor Substrate arranged on said insulation film, said islands for circuit element formation being compartmently formed by a trench extending to said insulation film; an insulation layer formed on an outer periphery portion of said islands for circuit element formation; and an island for capacitive coupling prevention formed of the material of said monocristalline semiconductor substrate, and disposed between said islands for circuit element formation, said island for capacitive coupling prevention being applied with an electric potential of constant.

Claim 7

In a semiconductor device as claimed in Claim 6, said islands for circuit element formation have an N⁺ emitter region, a P⁺ base region and an N⁻ collector region, a P⁺ diffusion region for extracting excessive carriers being formed in said N⁻ collector region.

Claim 8

In a semiconductor device as claimed in Claim 7, an oxide film is formed on a surface of said semiconductor substrate, and a plate electrode is provided on said oxide film between said P⁺ base region and said P⁺ diffusion region for extracting excessive carriers.

Claim 9

In a semiconductor device as claimed in Claim 8, a region of one conductivity type with high concentration is formed at a surface of said island for capacitive coupling prevention, and said region and said plate electrode are electrically connected, an electric potential of said island for capacitive coupling prevention being maintained in a high level.

Claim 10

In a semiconductor device as claimed in Claim 6, carrier concentration distribution in the interior of said island for capacitive coupling prevention is maintained equal to carrier concentration distribution in the interior of said islands for circuit element formation.

Claim 11

In a semiconductor device as claimed in Claim 10, carrier concentration distribution in the interior of said island for capacitive coupling prevention and carrier concentration distribution in the interior of said islands for circuit element formation become higher in carrier density at vicinity of the bottom as compared with vicinity of the surface.

Claim 12

In a semiconductor device in which plural circuit elements are formed on a silicon substrate provided on an insulation film, the semiconductor device comprising the following: first and second islands for circuit element formation formed of a material of said silicon substrate arranged on said insulation film; first and second insulation portions formed between said first and second islands for circuit element formation; and an island for capacitive coupling prevention disposed between said first and second insulation portions and applied thereto to be maintained in an electric potential of constant, said island for capacitive coupling prevention being formed of the material of said silicon substrate.

Claim 13

In a semiconductor device as claimed in Claim 12, said first and second insulation portions are composed of a silicon oxide film and polycrystalline silicon filled in the interior of said silicon oxide film.