Method and apparatus for timing control

Claim 2

A timing control apparatus according to claim 1 wherein said oscillator means (14) further comprises a summing means (32) for generating said output signal (16) to have a frequency and phase that is a function of a weighted sum of said plurality of control signals (13a,13b).

Claim 3

A timing control apparatus according to claim 2 wherein said summing means (32) generates said output signal (16) that has a frequency and phase that is substantially a function of a mathematical relationship 4*C1 + 7*C2 where C1 is a first one (13b) of said plural control signals (13a,13b) and C2 is a second one (13a) of said plural control signals (13a,13b).

Claim 4

A timing control apparatus according to claim 1 wherein said filter means (12) comprises a plurality of subfilter means (22,24,26), each responsive to said error signal (20c), for generating a respective one of said unique control signals (13a,13b) according to a selected transfer characteristic.

Claim 5

A timing control apparatus according to claim 4 wherein said subfilter means (22,24,26) comprises means for generating at least one of said control signals (13a,13b) based on a characteristic of a selected frequency spectrum of said error signal.

Claim 6

A timing control apparatus according to any one of claims 1, 4 or 5 wherein said filter means (12) comprises a third order low-pass filter (22, 24, 26) having at least two outputs, each of which generates a respective one of said control signals (13a,13b) as a function of the frequency of said error signal.

Claim 7

A timing control apparatus according to claim 6 wherein said third order low-pass filter (22,24,26) comprises means for generating at least one control signal as a function of a first portion of the frequency spectrum of said error signal, and at least one other control signal as a function of a second portion of the frequency spectrum of said error signal.

Claim 8

A timing control apparatus for generating a clock signal (120), comprising A. power supply means (116) for providing a power supply voltage level, B. current source means (112) coupled to said power supply (116) for generating a reference current that is substantially independent of said power supply voltage, and C. switch means (114) coupled to said power supply (116) and to said current source (112) for generating said clock signal (120) to have a time period that is a function of a ratio of said power supply voltage level to said reference current.

Claim 9

A timing control apparatus according to claim 8 wherein said current source means (112) further comprises A. input means for receiving an input control signal (118), and B. voltage control means (124,126) coupled to said input means for controlling said reference current as a function of the voltage amplitude of said input control signal (118).

Claim 10

A timing control apparatus according to claim 8 or 9 wherein said switch means (114) comprises means for decreasing said clock signal time period as a function of an increase in said power supply voltage level.

Claim 11

A timing control apparatus according to claim 8 or 9 wherein said switch means (114) comprises means for increasing said clock signal time period as a function of a decrease in said power supply voltage level.

Claim 12

A timing control apparatus according to any one of claims 8 to 11 wherein said switch means is a ring oscillator comprised of an odd number of CMOS inverter circuits (114) connected in series.

Claim 13

A timing control apparatus for generating a plurality of time-delayed signals (272a,272b,272c) that are coordinated to an input signal (18), comprising A. delay means (270) for generating said plurality of time-delayed signals (272a,272b,272c), B. comparator means (20), coupled to said delay means (270), responsive to said input signal (18) and to one of said time-delayed signals (272a) for generating an error signal representative of a difference in phase and frequency therebetween, C. filter means (12) coupled to said comparator means (20), for receiving said error signal and generating a plurality of unique control signals (13a,13b), wherein each control signal (13a,13b) has a voltage amplitude with a selected mathematical relationship to said difference in phase and frequency. D. oscillator means (14) coupled to said filter means (12) for responding to said plurality of control signals (13a,13b) for generating an output signal (16) to have a frequency and phase that is a function of said plural control signals (13a,13b), and, E. wherein said delay means (270) couples to said oscillator means (14), for receiving said output signal (16) and generating said plurality of time-delayed signals (272a,272b,272c) having a frequency substantially equal to that of said output signal (16) and having a selected time-delay with respect thereto.

Claim 14

A timing control apparatus for coordinating the delay of information signals output from an electronic circuit in response to an input clock signal, comprising A. delay means for generating a time-delayed signal, B. comparator means (20), coupled to said delay means, responsive to said input clock signal (18) and to said time-delayed signal for generating an error signal (20c) representative of a difference in phase and frequency therebetween, C. filter means (12) coupled to said comparator means, for receiving said error signal and generating a control signal, wherein said control signal has a voltage amplitude with a selected mathematical relationship to said difference in phase and frequency, D. oscillator means (14) coupled to said filter means (20) for responding to said control signal and generating an output signal having a frequency and phase that is a function of said control signal, E. circuit means (270) coupled to said oscillator means (14) for generating said information signals, said circuit means including i) generation means for receiving said output signal to generate said information signals coordinated to said output signal, and ii) buffer means for outputting said information signals from said circuit means, said buffer means having a characteristic delay, and iii) wherein said delay means couples to said oscillator means to receive said output signal for generating said time-delayed signal to have a frequency substantially equal to that of said output signal and to have a time delay related to the characteristic delay of said buffer means.

Claim 15

A timing control apparatus for time-delaying a clock signal, comprising A. clock input means for receiving said clock signal, B. current source means (274) for generating a reference current, and C. delay means (270) coupled to said current source means (274) and coupled to said clock input means for delaying said clock signal (16) as a function of said reference current.

Claim 16

A timing control apparatus according to claim 15 wherein said current reference further comprises A. control input means for receiving an input control signal (13a,13b), and B. voltage control means (28) coupled to said control input means for controlling said reference current as a function of the voltage amplitude of said input control signal (13a,13b).

Claim 17

A timing and control apparatus according to claim 16 wherein said delay means (270) comprises an inverter circuit coupled to said clock input means and that has an output coupling to transmit said delayed clock signal (272a,272b,272c).

Claim 18

A timing and control apparatus according to claim 15 wherein said delay means comprises a plurality of inverter circuits (276a,276b,276c) connected in series and wherein each inverter circuit has an output coupling to transmit one of said delayed clock signals (272a,272b,272c).

Claim 19

A timing control apparatus according to claim 18 wherein said plurality of inverter circuits (276a,276b,276c) connected in series comprises of at least two different size inverter circuits dimensioned to delay said clock signal (16) by at least two different time durations.