EP0609497A2
Expired / Lapsed
EP
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A device and method for maintaining a high voltage for low power applications
Assignee: UMC Japan Co Ltd
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Filing: 1993-10-27
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Granted: —
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Expires: 2013-10-27
Abstract
Abstract A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage (VCCP) for low power applications in an integrated circuit. The circuit includes separate standby circuits (110, 300, 478) and active circuits (200, 478', 500) for pumping V CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V CCP . The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain the high voltage (V CCP ). The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V CCP while minimizing power consumption in DRAM.
Inventors
- 👤 Michael Cordoba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:11
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/146
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
73 words
A voltage generator for maintaining a high voltage (VCCP) of a memory device comprising a low-power standby circuit (110, 300, 478) coupled to monitor said high voltage (VCCP) and pump charge to maintain said high voltage (VCCP), and an active circuit (200, 478', 500) coupled to pump charge to maintain said high voltage (VCCP), said active circuit (200, 478', 500) having a first input (14) for receiving an active circuit enabling signal (RASBP).
Claim 2
Dependent Claim
86 words
The voltage generator of Claim 1 wherein said standby circuit (110, 300, 478) includes a standby voltage regulator (110) coupled to monitor said high voltage (VCCP) and to output a standby clock enabling signal (PUMP) when said high voltage (VCCP) varies from a predetermined level, a standby clock circuit (300) responsive to the standby clock enabling signal (PUMP) for generating standby clock signals (CP1-CP5), and a standby pump circuit (478) responsive to the standby clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
Claim 3
Dependent Claim
35 words
The voltage generator of Claim 2 wherein the standby clock circuit (300) is a self-timed clock circuit which ignores the standby clock enabling signal (PUMP) during a second cycle of the standby pump circuit (478).
Claim 4
Dependent Claim
115 words
The voltage generator of any preceding claim wherein said active circuit includes an active voltage regulator (200) coupled to monitor said high voltage (VCCP) and having said first input (14) to receive the active circuit enabling signal (RASBP), said active voltage regulator (200) outputting an active clock enabling signal (PUMPA) when enabled by the active circuit enabling signal (RASBP) and when said high voltage (VCCP) varies from a predetermined level, at least one active clock circuit (500) responsive to the active clock enabling signal (PUMPA) for generating active clock signals (CP1-CP5), and at least one active pump circuit (478') responsive to the active clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
Claim 5
Dependent Claim
36 words
The voltage generator of Claim 4 wherein the at least one active clock circuit (500) is a self-timed clock circuit which ignores the active clock enabling signal (PUMPA) during a second cycle of the pump (478').
Claim 6
Dependent Claim
67 words
The voltage generator of Claim 1 wherein said active circuit (200, 478', 500) includes at least one active clock circuit (500) responsive to the active circuit enabling signal (PUMPA) for generating active clock signals (CP1-CP5) when receiving the active circuit enabling signal (RASBP); and at least one active pump circuit (478') responsive to the active clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
Claim 7
Dependent Claim
232 words
A voltage generator for maintaining a high voltage (V CCP ) in a DRAM comprising a standby circuit having a standby voltage regulator (110), a standby clock circuit (300), and a standby pump (478) which operates during a first cycle and a second cycle, said standby voltage regulator (110) being coupled to monitor the high voltage (V CCP ) and output a standby clock enabling signal (PUMP) when the voltage varies from a predetermined level, said standby clock circuit (300) being responsive to the standby clock enabling signal (PUMP) for generating standby clock signals (CP1-CP5) and being self-timed to ignore the standby clock enabling signal (PUMP) during the second cycle of the standby pump (478), said standby pump circuit (478) being coupled to receive said standby clock signals (CP1-CP4) for pumping charge to alter the high voltage (V CCP ), an active circuit having at least one active clock (500), and at least one active pump (478') which operates during a first cycle and a second cycle, said at least one active clock circuit (500) being responsive to an enabling signal (PUMPA) for generating active clock signals (CP1-CP5) and being self-timed to ignore the enabling signal (PUMPA) during a second cycle of the pump, and said at least one active pump circuit (478') being responsive to the active clock signals (CP1-CP5) for pumping charge to alter the high voltage (V CCP ).
Claim 8
Dependent Claim
72 words
The voltage generator of Claim 7, further including an active voltage circuit regulator (200) being coupled to monitor the high voltage (V CCP ) and including a first input (14) to receive an active circuit enabling signal (RASBP), said active voltage regulator (200) outputting said active clock enabling signal (PUMPA) when enabled by the active circuit enabling signal (RASBP) and when the high voltage (V CCP ) varies from a predetermined level.
Claim 9
Dependent Claim
35 words
The voltage generator of Claim 4 or 7 further including a second active clock circuit (500) responsive to the enabling signal (PUMPA) and a second clock enabling (2KREFPAD) signal for generating active clock signals (CP1-CP5).
Claim 10
Dependent Claim
29 words
The voltage generator of Claim 4 or 7 further including a second active pump (478') responsive to said active clock signals (CP1-CP5) generated by said second active clock (500).
Claim 11
Independent Claim
69 words
A method for maintaining a high voltage (VCCP) in a memory device comprising continuously monitoring said high voltage (VCCP) for a drop in voltage, and intermittently monitoring said high voltage (VCCP) for a drop in voltage, wherein the step of intermittently monitoring said high voltage (VCCP) is performed independently of the step of continuously monitoring said high voltage (VCCP) whenever a word line of said memory device is driven.
Claim 12
Dependent Claim
97 words
The method for maintaining a high voltage (VCCP) in a memory device of Claim 11 wherein the step of continuously monitoring is performed by a standby circuit including a standby voltage regulator (110) coupled to monitor said high voltage and to output a standby clock enabling signal (PUMP) when the voltage varies from a predetermined level, a standby clock circuit (300) responsive to the standby clock enabling signal (PUMP) for generating standby clock signals (CP1-CP5), and a standby pump circuit (478) responsive to the standby clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
Claim 13
Dependent Claim
131 words
The method for maintaining a high voltage (VCCP) in a memory device of Claim 11 wherein the step of intermittently monitoring said high voltage (VCCP) is performed by an active circuit including an active voltage regulator (200) coupled to monitor said high voltage (VCCP) and including said first input (14) to receive the enabling signal (RASBP), said active voltage regulator (200) outputting an active clock enabling signal (PUMPA) when enabled by the enabling signal (RASBP) and when said high voltage (VCCP) varies from a predetermined level, at least one active clock circuit (500) responsive to the active clock enabling signal (PUMPA) for generating active clock signals (CP1-CP5), and at least one active pump circuit (478') responsive to the active clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
Claim 14
Dependent Claim
75 words
The method for maintaining a high voltage (VCCP) in a memory device of Claim 11 wherein the step of intermittently monitoring said high voltage (VCCP) is performed by an active circuit including at least one active clock circuit (500) responsive to an enabling signal (PUMPA) for generating active clock signals (CP1-CP5), and at least one active pump circuit (478') responsive to said active clock signals (CP1-CP5) for pumping charge to alter said high voltage (VCCP).
References Cited (Backward Citations)
No citation records indexed.
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