EP0606912A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Polyphase clock generation circuit
Assignee: NEC Corp
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Filing: 1994-01-13
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Granted: —
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Expires: 2014-01-13
Abstract
Abstract A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.
Inventors
- 👤 Koichi C/O Nec Corporation Hiratsuka
- 👤 Hiroshi C/O Nec Corporation Hikichi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/06; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/1508; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
108 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; a clock driver including a P-channel field-effect transistor with a source connected to the first power source voltage terminal, and an N-channel field-effect transistor with a source connected to the second power source voltage terminal and a drain connected to a drain of the P-channel field-effect transistor; and clock driver driving means for turning on the P-channel field-effect transistor and the N-channel field-effect transistor alternately and independently of each other so that the P-channel field-effect transistor and the N-channel field-effect transistor may not have an ON-state simultaneously with each other.
Claim 2
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 1 wherein the second power source voltage terminal is grounded.
Claim 3
Dependent Claim
312 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical OR means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical OR means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.
Claim 4
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 3 wherein the second power source voltage terminal is grounded.
Claim 5
Dependent Claim
312 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical AND means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical AND means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.
Claim 6
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 5 wherein the second power source voltage terminal is grounded.
Claim 7
Dependent Claim
314 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means, a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical OR means by a first delay time; and second variable delay means for delaying the output signal of the second logical OR means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.
Claim 8
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 7 wherein the second power source voltage terminal is grounded.
Claim 9
Dependent Claim
39 words
The polyphase clock generation circuit as claimed in claim 7 further comprising delay time setting means for setting the first delay time of the first variable delay means and the second delay time of the second variable delay means.
Claim 10
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 9 wherein the second power source voltage terminal is grounded.
Claim 11
Dependent Claim
314 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to the drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical AND means by a first delay time; and second variable delay means for delaying the output signal of the second logical AND means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.
Claim 12
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 11 wherein the second power source voltage terminal is grounded.
Claim 13
Dependent Claim
39 words
The polyphase clock generation circuit as claimed in claim 11, further comprising delay time setting means for setting the first delay time of the first variable delay means and the second delay time of the second variable delay means.
Claim 14
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 13 wherein the second power source voltage terminal is grounded.
Claim 15
Dependent Claim
338 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, delay means for delaying the output signal of the logical OR means by a predetermined delay time, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.
Claim 16
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 15 wherein the second power source voltage terminal is grounded.
Claim 17
Dependent Claim
336 words
A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, variable delay means for delaying the output signal of the logical OR means, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the variable delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the variable delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.
Claim 18
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 17 wherein the second power source voltage terminal is grounded.
Claim 19
Dependent Claim
32 words
The polyphase clock generation circuit as claimed in claim 17 further comprising delay time setting means for setting delay times of the variable delay means which constitute the plurality of outputting means.
Claim 20
Dependent Claim
19 words
The polyphase clock generation circuit as claimed in claim 19 wherein the second power source voltage terminal is grounded.
References Cited (Backward Citations)
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