Maximum likelihood data detector

Claim 1

A digital data demodulating apparatus comprising: a sampling circuit for sampling a received signal at a speed N × K (N > 1, K > 1; integers) times a symbol rate, classifying combinations of sequences having symbol intervals sampled at K different sample timings into N combinations, and outputting received signal sequences sampled at the same speeds as N × K symbol speeds; N received signal sequence selection circuits for receiving received signal sequences, of a plurality of received signal sequences output from said sampling circuit, which are sampled at the K different timings, estimating channel impulse responses from the respective received signal sequences, obtaining and outputting channel state data on the basis of the respective estimated channel impulse response values, and outputting a control pulse for controlling selection of demodulation received signal sequence candidates from the received signal sequences sampled at the K different timings on the basis of the respective estimated channel impulse response values, and the estimated channel impulse response values estimated from the demodulation received signal sequence candidates; a received signal sequence selection controller for receiving the channel state data respectively output from said N received signal sequence selection circuits, and outputting a switch control signal for selecting a received signal sequence to be demodulated on the basis of the channel state data; N selectors for receiving the control pulse and the plurality of received signal sequences sampled at the N difference timings, selecting demodulation received signal sequence candidates from the plurality of received signal sequences, sampled at the K different timings, on the basis of the control pulse, and outputting the selected candidates; a first switch for receiving the outputs from said N selectors and the switch control pulse, and selecting and outputting the received signal sequence to be demodulated from the outputs from said N selectors on the basis of the switch control pulse; a second switch for receiving the switch control pulse and the estimated channel impulse response values estimated from the demodulation received signal sequence candidates output from said N received signal sequence selection circuits, and selecting and outputting an estimated channel impulse response value, estimated from the received signal sequence to be demodulated, from the estimated channel impulse response values estimated from the demodulation received signal sequence candidates, on the basis of the switch control pulse; and a demodulation circuit for performing demodulation upon reception of the outputs from said first and second switches.