EP0602791A2
Expired / Lapsed
EP
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Apparatus and method for booting a multiple processor system having a global/local memory architecture
Assignee: International Business Machines Corp
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Filing: 1993-11-01
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Granted: —
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Expires: 2013-11-01
Abstract
Abstract An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.
Inventors
- 👤 William Rudolph Hardell, Jr.
- 👤 James Dodd Henson, Jr.
- 👤 Oscar Reid Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 18:11
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
90 words
Apparatus for booting a multi-processor computer system having shared global memory (18) and processor-local memory (9, 11, 12, 13), comprising: means for asynchronously starting multiple processors (1, 2, 3, 4); and means for synchronizing to a master clock a signal in the start sequence of each of said multiple processors, wherein the means for synchronising comprises reset circuitry (21, 22) for synchronising a commonly distributed start signal and processor individualised resource start sequences, the rest circuitry being adapted to distribute reset circuit signals to reset both local and global memory.
Claim 2
Dependent Claim
24 words
Apparatus according to claim 1, further comprising: means for testing (6, 7) global memory by a first processor in synchronism to the master clock.
Claim 3
Dependent Claim
33 words
Apparatus according to claim 2, wherein said first processor is selected to test the global memory (18) based on said first processor being first among the processors to complete an internal test sequence.
Claim 4
Dependent Claim
21 words
Apparatus according to claim 3, further comprising: means for decoupling nonselected processors from global memory during the test of global memory.
Claim 5
Dependent Claim
41 words
Apparatus according to claim 3 or claim 4, wherein the means for testing the global memory using a selected processor further comprises a means for synchronising the global memory reset and the global memory test signals to the master clock means.
Claim 6
Dependent Claim
43 words
Apparatus according to any one of the preceding claims, wherein the means for asynchronously starting multiple processors includes means for individually starting each processor, the asynchronous start sequence in each processor involving stepping each processor through a multiple stage individually clocked start sequence.
Claim 7
Independent Claim
69 words
A method of booting a multi-processor computer system having shared global memory and processor-local memory, comprising: asynchronously starting the multiple processors (1, 2, 3, 4) and synchronising to a master clock a signal in a start sequence of each of said multiple processors, including synchronising a commonly distributed start signal and processor-individualised resource start sequences using reset circuitry, reset signals being distributed to reset both local and global memory.
Claim 8
Dependent Claim
25 words
A method according to claim 7, further comprising the step of: testing the global memory by a first processor in synchronism with the master clock.
Claim 9
Dependent Claim
37 words
A method according to claim 8, further comprising the step of: selecting one of the processors to test the global memory based on said one processor being first among the processors to complete an internal test sequence.
Claim 10
Dependent Claim
35 words
A method according to claim 9, wherein the step of testing the global memory by a selected processor further comprises the synchronisation of the global memory test signals and reset signals to the master clock.
Claim 11
Independent Claim
40 words
A method according to any one of claims 7 to 10, wherein the step of asynchronously starting the multiple processors includes: starting each processor individually, the asynchronous start sequence in each processors involving a multiple stage individually clocked start sequence.
References Cited (Backward Citations)
No citation records indexed.
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