EP0600815A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A high resolution programmable pulse generator
Assignee: International Business Machines Corp
•
Filing: 1993-11-04
•
Granted: —
•
Expires: 2013-11-04
Abstract
Abstract A programmable pulse generator that uses high resolution programmable delay circuits (HRPDCs) as building blocks, each of which is capable of changing timing "on-the-fly", i.e., modifying the programmable delay within one tester cycle and without the limitations of existing delay circuits. The pulse generator comprises a timing control array that is subdivided into three components providing coarse delay, fine delay and extra-fine delay; a plurality of timing generators respectively controlled by the timing control array, each generator further comprising a plurality of HRPDCs, programmable delay circuits, and fixed delay blocks appropriately combined to modify pulse delay and pulse edges within each cycle.
Inventors
- 👤 John Edward Dickol
- 👤 Dinh Lien Do
- 👤 Algirdas Joseph Gruodis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/135; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/00071; H03K2005/0015; H03K2005/00163; H03K2005/00176; H03K2005/00182
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
164 words
A programmable delay circuit, comprising: a 1-to-N demultiplexer having an input for receiving a clock signal with a cycle time, said demultiplexer having N outputs; N logic gates connected in series to each other, each of said gates being respectively controlled by one of said N outputs of said demultiplexer; and a register having inputs for accepting signals that define a predetermined delay and outputs that drive said demultiplexer, for propagating said clock signal through at least one of said gates, and for outputting at the last of said N logic gates a signal which is delayed with respect to said clock signal, wherein said predetermined delay is reprogrammed to a new delay after a time interval that is equal to the time required for said clock signal to propagate through said demultiplexer, said time interval being less than the cycle time of said clock signal and less than the time required for said clock signal to propagate through all said N logic gates.
Claim 2
Dependent Claim
14 words
The circuit as recited in claim 1, wherein the logic gates are OR gates.
Claim 3
Dependent Claim
32 words
The circuit as recited in claim 1, wherein the logic gates are AND gates and wherein signals provided by said demultiplexer to be inputted into each of said AND gates are inverted.
Claim 4
Dependent Claim
61 words
The circuit as recited in claim 1, wherein the programmable delay is: t total = t fixed x (S+1) t block , wherein t total is the delay through said programmable delay circuit, t fixed is the delay through said demultiplexer, t block is the delay through one of said logic gates, and S is a number representing said predetermined delay.
Claim 5
Dependent Claim
181 words
A high resolution programmable delay circuit (HRPDC) having a delay which is at least an order of magnitude lower than the delay of a logic gate, and which provides timing-on-the-fly capabilities, comprising: a first logic gate having an input for receiving a signal provided by a clock and an output; a second logic gate having an input connected to the output of the first logic gate and an output for providing a signal which is delayed with respect to the signal provided by the clock; means for loading connected to the output of the first logic gate comprising at least one loading block, each of said at least one loading blocks having a loading input and a control input, wherein the loading input is connected to the output of the first logic gate, the control input provides a control signal which determines the amount of loading on said first logic gate, thereby controlling the amount of delay by which a signal outputted at the output of said second logic gate is delayed with respect of the signal provided by the clock.
Claim 6
Dependent Claim
55 words
The high resolution programmable delay circuit as recited in claim 5, wherein each of said loading blocks comprises a current switch emitter follower circuit having a plurality of inputs, one of said inputs is the control input and the remaining of said plurality of inputs are connected to each other to form the loading input.
Claim 7
Dependent Claim
100 words
A compounded high resolution programmable delay circuit having a clock input, a control input and an output, said compounded high resolution programmable delay circuit comprising: 2 M high resolution programmable delay circuits (HRPDCs), wherein each of said HRPDCs has a clock input, a control input and an output, said HRPDCs are connected to each other in series by connecting the output of one of said HRPDCs to the clock input of the next HRPDC, and wherein each of the control inputs of each of said HRPDC are connected to each other to form the control input of the compounded circuit.
Claim 8
Dependent Claim
114 words
The compounded high resolution programmable delay circuit as recited in claim 7, further comprising 2 M -1 delay blocks, each of said blocks having an input and an output, the input of the first of said delay blocks is connected to the control input of the first of said HRPDCs, the output is attached to the control input of the second of said HRPDCs, and the 2 M -1 delay block is connected to the control input of the 2 M -1 HRPDC and the output of the 2M₋₁ said delay block is attached to the control input of the 2 M HRPDC, thereby moving the control signal in step with the clock signal.
Claim 9
Dependent Claim
202 words
A programmable delay structure, comprising: N compounded HRPDCs comprising each 2 M HRPDCs, each of said compounded HRPDCs having a clock input, a control input and an output, wherein said compounded HRPDCs are connected to each other in series by connecting the output of one of said compounded HRPDC to the clock input of the next compounded HRPDC, wherein the first of said compounded HRPDCs includes 2⁰ HRPDCs, the second includes 2¹ HRPDCs, and the Nth of said compounded HRPDCs includes 2 N-1 HRPDCs, and wherein the delay through the programmable delay structure is: t total = t fixed + D x t HRPDC in which t total is the delay through the structure, t fixed is the minimum delay through all the HRPDCs, and t HRPDC is the difference between the delay through the HRPDC when the control input of said HRPDC is in a predetermined binary state and the delay through said HRPDC when the control input is in the opposite binary state, and D is a number that corresponds to the number of HRPDCs which are in an active state, and wherein the control input of the compounded HRPDC is connected to the control input of the first HRPDC.
Claim 10
Dependent Claim
33 words
The programmable delay structure as recited in claim 9, wherein each of said HRPDCs has a control input, so that the predetermined binary state is determined by setting the control input to 0.
Claim 11
Dependent Claim
97 words
The programmable delay structure as recited in claim 9, further comprising N-1 delay blocks Dly, each having an input and an output, wherein the input provides signals that specify a predetermined delay, and the output at the mth block is attached to said control input of the (m+1)th of said compounded HRPDCs to align the signals at said clock inputs with said control inputs of said compounded HRPDCs, wherein the delay of the mth block is: Dly m = t D x (2 m - 1) wherein t D is the delay through one of said HRPDCs.
Claim 12
Dependent Claim
185 words
A programmable pulse generator for providing a linear, high resolution delay over a wide range of delays, for providing delay overlap, and for shaping an output pulse with edges of predefined shape, comprising: a timing control array having a plurality of inputs and outputs, each input is connected to a respective data line for selecting a predetermined delay to be generated, said array having address lines for determining an address; N timing generators, each having a clock input driven by clocking means, a plurality of control input lines connected to the outputs of said timing control array and an output to provide a signal which is delayed with respect to said clock input signal; and a data formatter having N inputs and an output, wherein each of said inputs is respectively driven by one of said N timing generators outputs, and wherein each of said inputs controls the position of a signal's rising or falling edge at said output, said data formatter combines signals at said N inputs into pulses having rising and falling edges that are delayed with respect to said input clock signal.
Claim 13
Dependent Claim
62 words
The programmable pulse generator as recited in claim 12, further comprising a timing control array that is partitioned into three arrays to provide coarse delay provided by said coarse delay generator, fine delay provided by said programmable delay circuit and extra-fine delay provided by said programmable delay structure, each of said arrays drives its own separate set of said timing control generators.
Claim 14
Dependent Claim
106 words
The programmable pulse generator as recited in claim 13, wherein each of said timing control generators further comprises: a coarse delay generator that drives a programmable delay structure, said structure drives a programmable delay circuit, and wherein said coarse delay generator is provided with plural control inputs that are connected to the outputs of said coarse delay array; said programmable delay structure is provided with plural control inputs connected to the outputs of said extra fine array; and said programmable delay circuit is provided with plural control inputs connected to the outputs of said fine delay array and which output is connected to a data formatter.
Claim 15
Dependent Claim
164 words
The programmable pulse generator of claim 14, further comprising: a first address delay block having inputs connected to said address lines of said coarse timing control array and outputs connected to said address lines of said extra fine timing control array, said first address delay block delaying each of said address lines by a time interval which is equal to the minimum delay through said coarse delay generator, thereby aligning said extra fine timing control array outputs with said programmable delay structure clock inputs, and a second address delay block having inputs connected to said address lines of said extra fine timing control array and outputs connected to said address lines of said fine timing control array, said second address delay block delaying each of said address lines by a time interval which is equal to the minimum delay through said extra fine delay generator, thereby aligning said fine timing control array outputs with said programmable delay circuit clock inputs, thereby permitting timing-on-the-fly capabilities.
Claim 16
Dependent Claim
152 words
A high resolution programmable delay circuit having a delay which is at least an order of magnitude lower than the delay of a logic gate, and which provides timing-on-the-fly capabilities, comprising: a logic gate having an input for receiving a signal provided by a clock and one output for providing a signal which is delayed with respect to the clock signal; means for loading connected to the output of the logic gate comprising at least one loading block, each of said at least one loading blocks having: a loading input and a control input, the loading input is connected to the output of the logic gate, the control input provides a control signal which determines the amount of loading on said logic gate, thereby controlling the amount of delay by which a signal outputted at the output of said logic gate is delayed with respect of the signal provided by the clock.
Claim 17
Dependent Claim
55 words
The high resolution programmable delay circuit as recited in claim 16, wherein each of said loading blocks comprises a current switch emitter follower circuit having a plurality of inputs, one of said inputs is the control input and the remaining of said plurality of inputs are connected to each other to form the loading input.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.