Patent EP0352125A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0597315A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Switched capacitor D/A converter

Assignee: RCA Licensing Corp
•
Filing: 1993-10-26
•
Granted: —
•
Expires: 2013-10-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node. Following the data transfer onto the binary weighted capacitors ,the switching transistors are precharged and, concurrently the N capacitors are connected in parallel to produce an analog voltage corresponding to the serial data.

Inventors

  • 👤 Andrew Gordon Francis Dingwall
  • 👤 Sherman Weisbrod

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 20:16
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/42; G; G09; G09G; G09G3/00; G09G3/20; G09G3/2007; G09G3/2011; G09G3/34; G09G3/36; G09G3/3611; G09G3/3685; G09G3/3688; H03; H03M; H03M1/00; H03M1/12; H03M1/66; H03M1/74; H03M1/80; H03M1/802; H03M1/804; G09G2310/00; G09G2310/02; G09G2310/0264; G09G2310/027; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 269 words
A digital-to-analog converter (DAC) for converting a set of N data bits to an analog voltage comprising: N capacitors (CO-C5), one capacitor for each one of said N data bits; each capacitor having first and second plates; and means connecting the first plate of each capacitor to an output node; characterized by: N switching transistors (M26-M25) one for each one of said N data bits, each one of said N switching transistors having first and second electrodes defining the ends of a conduction path and a gate electrode, each gate electrode having associated therewith a relatively small capacitance; means connecting the conduction path of each switching transistor between the second plate of its associated capacitor and a first power terminal (ground); an input node (3) adapted to receive serially supplied digital data signals during a data load interval and a precharge signal during a precharge interval; N selectively enabled data transfer paths, (M10, M30, ...M15,M35) one data transfer path per each one of said N switching transistors, each data transfer path connected between said input node and the gate electrode of its associated switching transistor; means (CSj;BO-B5) for selectively turning-on said N data transfer paths, one at time, during said data load interval for selectively sampling the digital data signals and for applying and storing a voltage corresponding to each one of said digital data signals on the gate of a corresponding one of said N switching transistors; and means (M3) for selectively applying a voltage across said capacitors for charging them in accordance with the data responsive voltage levels present on the gate of their respective switching transistors.
Claim 2
Dependent Claim 269 words
A digital-to-analog converter (DAC) for converting a set of N data bits to an analog voltage comprising: N capacitors (CO-C5), one capacitor for each one of said N data bits; each capacitor having first and second plates; and means connecting the first plate of each capacitor to an output node; characterized by: N switching transistors (M26-M25) one for each one of said N data bits, each one of said N switching transistors having first and second electrodes defining the ends of a conduction path and a gate electrode, each gate electrode having associated therewith a relatively small capacitance; means connecting the conduction path of each switching transistor between the second plate of its associated capacitor and a first power terminal (ground); an input node (3) adapted to receive serially supplied digital data signals during a data load interval and a precharge signal during a precharge interval; N selectively enabled data transfer paths, (M10, M30, ...M15,M35) one data transfer path per each one of said N switching transistors, each data transfer path connected between said input node and the gate electrode of its associated switching transistor; means (CSj;BO-B5) for selectively turning-on said N data transfer paths, one at time, during said data load interval for selectively sampling the digital data signals and for applying and storing a voltage corresponding to each one of said digital data signals on the gate of a corresponding one of said N switching transistors; and means (M3) for selectively applying a voltage across said capacitors for charging them in accordance with the data responsive voltage levels present on the gate of their respective switching transistors.
Claim 3
Dependent Claim 36 words
A converter in accordance with claim 1 wherein, during each precharge interval, the gate capacitance of each one of said N switching transistors is precharged to a turn-on-level, and said N capacitors are connected in parallel.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag