EP0596417A2 — Memory controller, reproducing apparatus, mountin…

Claim 1

Independent Claim 154 words

A disc reproducing apparatus in which after the sector consisting of at least the sync data, header data, and digital data, and the data stored in a recording medium (3) is sequentially read for said each sector and is written once in a memory (10), the data stored in said memory (10) is sequentially read for each sector and is reproduced, comprising: memory control means (8) for controlling the write/read of said digital data to said memory (10); and control means (9) for controlling the operation of said memory control means (8): and wherein; said memory control means (8) has a counter mode control means (29) for switching the mode according to the read/write control signal transferred from said control means (9) and/or the state of said data, and a read out address generating means (27, 28) for generating a read out address according to the mode from said counter mode control means (29).

Claim 2

Dependent Claim 154 words

A disc reproducing apparatus in which after the sector consisting of at least the sync data, header data, and digital data, and the data stored in a recording medium (3) is sequentially read for said each sector and is written once in a memory (10), the data stored in said memory (10) is sequentially read for each sector and is reproduced, comprising: memory control means (8) for controlling the write/read of said digital data to said memory (10); and control means (9) for controlling the operation of said memory control means (8): and wherein; said memory control means (8) has a counter mode control means (29) for switching the mode according to the read/write control signal transferred from said control means (9) and/or the state of said data, and a read out address generating means (27, 28) for generating a read out address according to the mode from said counter mode control means (29).

Claim 3

Dependent Claim 98 words

A disc reproducing apparatus according to claim 1, wherein: said counter mode control means (29) switches the mode to one of three mode; the round mode in which the internal address of said memory (10) generated by said read out address generating means (27, 28) specify the address in the same area repeatedly; the straight mode in which the address of the next area after the specification of address in one area terminates is specified; and the re-try mode in which the address in the front area after the specification of address in one area terminates is specified.

Claim 4

Dependent Claim 176 words

A disc reproducing apparatus according to claim 2, wherein: said control means (9), comprises: a first comparison means for comparing the data size stored in said memory (10) with the first predetermined value; and a second comparison means for comparing the data size stored in said memory (10) with the second predetermined value smaller than said first predetermined value: and wherein: in the case where said read out address generating means (27, 28) is in said straight mode, when it is judged that the data size stored in said memory (10) is more than a first predetermined value as a result of said first comparison means or said data is not the target data, switches to said round mode; and in the case where said read out address generating means (27, 28) are in said round mode, when it is judged that the data size stored in said memory (10) is less than a second predetermined value as a result of said second comparison means or the target data is read, switches to said straight mode.

Claim 5

Dependent Claim 55 words

A disc reproducing apparatus according to claims 2 or 3, wherein: said control means (9), in the case where said read out address generating means (27, 28) is in said straight mode, when it is detected that an error is contained in the data written to said storage means (10), switches to said re-try mode.

Claim 6

Dependent Claim 64 words

A disc reproducing apparatus according to any of claims 1 to 4, wherein: said sector data type is one of the link sector, the sub-data, and the compression data; said counter mode control means (29) selects the round mode when said sector data is the link sector or the sub-data; and the straight mode is selected when said sector data is the compression data.

Claim 7

Dependent Claim 177 words

A memory control circuit (8) for controlling memory (10) in which after the stored data is sequentially read from the recording medium (3) for each sector unit consisting of at least the sync data, header data, and digital data, and is written once in a memory, the data stored in said memory is sequentially read for each sector, comprising: a signal process means (21-25) for extracting the sink data of said sector and for judging the status of said sector; a counter mode control means (29) for controlling the mode according to the data from the control means and said status; a read out address generating means (27, 28) for generating the read out address in said memory (10) according to the mode from said counter mode control means (29) and the sync data from said signal process means (21-25); and a control means for controlling the write of data to the memory (10) or the read of data from the memory (10), according to the address specified by said read out address generating means (27, 28).

Claim 8

Dependent Claim 177 words

A memory control circuit (8) for controlling memory (10) in which after the stored data is sequentially read from the recording medium (3) for each sector unit consisting of at least the sync data, header data, and digital data, and is written once in a memory, the data stored in said memory is sequentially read for each sector, comprising: a signal process means (21-25) for extracting the sink data of said sector and for judging the status of said sector; a counter mode control means (29) for controlling the mode according to the data from the control means and said status; a read out address generating means (27, 28) for generating the read out address in said memory (10) according to the mode from said counter mode control means (29) and the sync data from said signal process means (21-25); and a control means for controlling the write of data to the memory (10) or the read of data from the memory (10), according to the address specified by said read out address generating means (27, 28).

Claim 9

Dependent Claim 78 words

A memory control circuit of claim 7, wherein said mode has three mode; the round mode in which the internal address of said memory (10) specify the address in the same area repeatedly; the straight mode in which the address of the next area after the specification of address in one area terminates is specified; and the re-try mode in which the address in the front area after the specification of address in one area terminates is specified.

Claim 10

Dependent Claim 134 words

A memory control circuit according to claim 7, wherein: said read out address generating means (27, 28), comprises; a sector count means (27B, 28B) for counting the sector number of data inputted with sector unit; a calculation means (27C, 28C) for converting the count value of said sector counter means (27B, 28B) from the sector number to the byte number; a byte counter means (27A, 28B) for counting up said added result for each 1 byte according to the count signal from said memory control means; and a addition means (27D, 28D) for adding the result of said calculation means (27C, 28C) and the result of said byte counter means (27A, 28A): and wherein: said read out address generating means (27, 28) further instructs said added result as the address in said memory (10).

Claim 11

Dependent Claim 30 words

A memory control circuit according to claim 8, wherein said byte counter means (27A, 28A) further comprises a reset means for resetting to "0" by input of said sync data.

Claim 12

Dependent Claim 24 words

A memory control circuit according to claims 8 or 9, wherein: said sector count means (27B, 28B) counts up according to said mode input.

Claim 13

Dependent Claim 47 words

A memory control circuit according to any of claims 8 to 10, wherein: said sector count means (27B, 28B) maintains the present counter value in said round mode, counts up the counter value in said straight mode, and counts down the counter value in said re-try mode.

Claim 14

Dependent Claim 191 words

A memory control method for controlling the memory (10) in which after the stored data is sequentially read out from the recording medium (3) for each sector unit consisting at least sync data, header data, and digital data, and is stored once in the memory (10), the data stored in said memory (10) is sequentially read out for each sector unit, comprising the steps of: initializing the address of the address generating circuit; controlling access near the target sector; instructing the memory control means (8) to the round mode; judging the generation of sync data; judging whether when the sync data is generated in said the step, it is the target sector or not; instructing said memory control means (8) to the straight mode when the sync data is the target sector in the above step; judging the generation of the sync data again; judging whether the sector data written just before is correct or not; instructing said memory control means (8) to the re-try mode when the sector data written just before is not correct in the above step; and controlling access to said sector data written just before again.

Claim 15

Dependent Claim 191 words

A memory control method for controlling the memory (10) in which after the stored data is sequentially read out from the recording medium (3) for each sector unit consisting at least sync data, header data, and digital data, and is stored once in the memory (10), the data stored in said memory (10) is sequentially read out for each sector unit, comprising the steps of: initializing the address of the address generating circuit; controlling access near the target sector; instructing the memory control means (8) to the round mode; judging the generation of sync data; judging whether when the sync data is generated in said the step, it is the target sector or not; instructing said memory control means (8) to the straight mode when the sync data is the target sector in the above step; judging the generation of the sync data again; judging whether the sector data written just before is correct or not; instructing said memory control means (8) to the re-try mode when the sector data written just before is not correct in the above step; and controlling access to said sector data written just before again.

Claim 16

Dependent Claim 60 words

A memory control method according to claim 12, further comprising the steps of: instructing said memory control means (8) to the straight mode, when the sector data written just before is correct in the above step for judging whether the sector data written just before is correct or not; and judging whether the data read out is terminated or not.

Claim 17

Dependent Claim 57 words

A memory control method according to claim 13, further comprising the step of: over-writing the new sector data in the same area repeatedly when the sync data is not the target sector in the step for judging whether the sync data is the target sector or not when the sync data is generated in the above step.

Memory controller, reproducing apparatus, mounting the same and method for controlling the same

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