EP0587443A2
Expired / Lapsed
EP
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Image processor and method
Assignee: Texas Instruments Inc
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Filing: 1993-09-10
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Granted: —
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Expires: 2013-09-10
Abstract
Abstract To enable high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operations such as MPEG etc, eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image information can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-bell operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.
Inventors
- 👤 Masashi Hashimoto
- 👤 Hirohisa Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 06:44
CPC Classifications
G; G11; G11C; G11C7/00; H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/436; H04N19/60; H04N19/61; H04N5/00; H04N5/14; H04N5/76; H04N5/907
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
63 words
An image processing method characterized by the following facts: one-picture image information is divided into multiple blocks in matrix form; the aforementioned multiple blocks are allocated to multiple memory arrays in such a way as to ensure that all of the blocks adjacent to an arbitrary block are stored in corresponding memory arrays that are different from that of the aforementioned arbitrary block.
Claim 2
Dependent Claim
92 words
The image processing method described in Claim 1, characterized by the fact that it has the following stages of operation: all of the image information is contained in one block or multiple blocks which at least partially overlap with an area, which has the same size as the aforementioned block in the image information address space and which is defined at an arbitrary position; the image information corresponding to the aforementioned area is extracted from the aforementioned read image information; for the aforementioned extracted image information, the half-bell processing is carried out.
Claim 3
Dependent Claim
39 words
The image processing method described in Claim 1 or 2 characterized by the fact that all of the image information stored in each block is written to or read out simultaneously as one row or one column of data.
Claim 4
Dependent Claim
63 words
A type of image processing device characterized by the following facts: one-picture image information is divided into multiple blocks in matrix form; the aforementioned multiple blocks are allocated to multiple memory arrays in such a way as to ensure that all of the blocks adjacent to an arbitrary block are stored in corresponding memory arrays different from that of the aforementioned arbitrary block.
Claim 5
Dependent Claim
170 words
A type of image processing device characterized by the fact that it has the following parts: multiple memory arrays which can perform independent memory access; a write means by which the unit image information divided into multiple blocks in matrix form in the information address space are stored in block units in any of the aforementioned memory arrays appropriately to ensure that all of the blocks adjacent to an arbitrary block are stored in corresponding memory arrays different from that of the aforementioned arbitrary block; a reading means which reads all of the image information contained in one block or multiple blocks which at least partially overlap with an area, which has the same size as the aforementioned block in the image information address space and which is defined at an arbitrary position, and which extracts the information corresponding to the aforementioned areas from the aforementioned read information; and a half-bell processing operation mean which performs the half-bell processing for the information extracted by means of the aforementioned reading means.
Claim 6
Dependent Claim
124 words
A half-bell processing method characterized by the fact that it consists of the following stages of operation: from the memory means storing one-picture image information, the pixels in the prescribed area assigned at an arbitrary site within the aforementioned picture are read by row or by column; the single row or single column of pixels read out in the above way are held, and the data for each pixel are output in a prescribed number of cycles with multiple bits in each cycle, from the lower bit; addition is performed for each position of the aforementioned output multiple bits for the adjacent pixels; the sums calculated for each position are combined to form the average value for the adjacent pixels of the prescribed number.
Claim 7
Dependent Claim
9 words
An image processor or method substantially as herein described.
References Cited (Backward Citations)
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