EP0585059A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Vertical memory cell processing and structure manufactured by that processing
Assignee: STMicroelectronics lnc USA
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Filing: 1993-08-19
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Granted: —
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Expires: 2013-08-19
Abstract
Abstract The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect. <IMAGE>
Inventors
- 👤 Mehdi Zamanian
- 👤 James Leon Worley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10B; H10B10/00
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
200 words
A method of forming a portion of a memory cell of a semiconductor integrated circuit; comprising the steps of: forming a first transistor over a portion of a substrate wherein the first transistor has a source/drain region; forming a first dielectric layer over the substrate and the first transistor, wherein the first dielectric layer has a first and a second opening exposing a portion of the source/drain region and a portion of a gate electrode of the first transistor, respectively; forming a first and a second interconnect region over a portion of the first dielectric layer and in the first and second openings; forming a second dielectric layer over the first and second interconnects and the first dielectric layer, wherein the second dielectric layer has a third opening exposing a portion of the second interconnect; forming a second transistor over the second dielectric layer and in the third opening; forming a third dielectric layer over the second transistor, wherein the third dielectric layer has a fourth opening exposing a portion of source and drain regions of the second transistor disposed over the second interconnect; and forming a first conductive layer over the third dielectric layer and in the fourth opening.
Claim 2
Dependent Claim
37 words
The method of claim 1, further comprising the steps of: etching the silicon substrate before forming the first transistor to form a pillar, wherein the first transistor is adjacent to and within the pillar and the substrate.
Claim 3
Independent Claim
205 words
A method of forming a portion of a memory cell of a semiconductor integrated circuit; comprising the steps of: etching a silicon substrate to form a pillar; forming a first transistor over a portion of the substrate adjacent to and within the pillar and the substrate; forming a first dielectric layer over the substrate and the first transistor, wherein the first dielectric layer has a first and a second opening exposing a portion of the pillar and a portion of a gate of the first transistor, respectively; forming a first and a second interconnect region over a portion of the first dielectric layer and in the first and second openings; forming a second dielectric layer over the first and second interconnects and the first dielectric layer, wherein the second dielectric layer has a third opening exposing a portion of the second interconnect; forming a second transistor over the second dielectric layer and in the third opening; forming a third dielectric layer over the transistor, wherein the third dielectric layer has a fourth opening exposing a portion of source and drain regions of the second transistor disposed over the pillar; and forming a first conductive layer over the third dielectric layer and in the fourth opening.
Claim 4
Dependent Claim
68 words
The method of claim 3 further comprising the steps of: forming a fourth dielectric layer over the first conductive layer and the third dielectric layer; etching a fifth opening in the third and fourth dielectric layers to expose a portion of one of the source and drain regions of the second transistor; and forming a second conductive layer over the fourth dielectric layer and in the fifth opening.
Claim 5
Dependent Claim
14 words
The method of claim 4 wherein the second conductive layer comprises a metal layer.
Claim 6
Dependent Claim
78 words
The method of claim 3 wherein the step of forming the first transistor comprises the following steps: forming a first gate oxide layer over the integrated circuit; forming a first N-type polysilicon layer over the gate oxide layer; patterning and etching the first polysilicon layer to form a first gate electrode exposing the pillar and a portion of the substrate; and implanting the pillar and the substrate with an N-type dopant to form N-type source and drain regions.
Claim 7
Dependent Claim
27 words
The method of claim 6 wherein the first and second interconnects are implanted with an N-type dopant to form an ohmic contact to the pillar and transistor.
Claim 8
Dependent Claim
107 words
The method of claim 3 wherein the step of forming the second transistor comprises the steps of: forming a second N-type polysilicon layer over the second dielectric layer and in the third opening; forming a second gate oxide layer over the second polysilicon layer; forming a third polysilicon layer over the second gate oxide layer; etching the third polysilicon layer to form a second gate electrode; and implanting the second and third polysilicon layers with a P-type dopant, wherein the second polysilicon layer comprises source and drain and channel regions of the second transistor and wherein the channel region remains N-type after the P-type dopant is implanted.
Claim 9
Independent Claim
283 words
A method of forming a portion of a memory cell of a semiconductor integrated circuit; comprising the steps of: etching a substrate to form a pillar; forming a first gate oxide layer over the substrate and the pillar; forming a first polysilicon gate electrode of a first transistor over a portion of the gate oxide adjacent to the pillar; implanting a dopant into the gate electrode, the pillar and the substrate, to form first source and drain regions of the first transistor in the substrate and pillar; forming a first dielectric layer over the substrate, the first gate and pillar wherein the first dielectric layer has a first and a second opening therethrough exposing a portion of the pillar and the first gate, respectively; forming an interconnect region in the first and the second opening; forming a second dielectric layer over the interconnect regions and the first dielectric; wherein the second dielectric has a third opening therethrough exposing a portion of the polysilicon interconnect region disposed over the pillar; forming a first polysilicon layer over the second dielectric layer and in the third opening; forming a second gate oxide and second polysilicon gate of a second transistor over a portion of the first polysilicon layer; implanting a dopant into the first polysilicon layer, wherein the first polysilicon layer forms a source, a drain and a channel region of the second transistor; forming a third dielectric layer over the second polysilicon gate and first polysilicon source/drain region having a fourth opening therethrough exposing a portion of the first polysilicon source/drain region disposed over the pillar; and forming a second polysilicon layer over a portion of the third dielectric layer and in the fourth opening.
Claim 10
Dependent Claim
29 words
The method of claim 9 wherein the first polysilicon gate electrode, pillar and a portion of the substrate is implanted with an N-type dopant to form an n-channel transistor.
Claim 11
Dependent Claim
61 words
The method of claim 9 further comprising the steps of: forming a fourth dielectric layer over the second polysilicon layer and the third dielectric layer; forming a fifth opening in the fourth dielectric layer and the third dielectric exposing a portion of the first polysilicon layer; and forming a conductive layer over the fourth dielectric layer and in the fifth opening.
Claim 12
Dependent Claim
12 words
The method of claim 11 wherein the conductive layer comprises a metal.
Claim 13
Dependent Claim
12 words
The method of claim 10 wherein the polysilicon interconnect region is N-type.
Claim 14
Dependent Claim
21 words
The method of claim 9 wherein the first polysilicon layer and the second polysilicon gate are implanted with an N-type dopant.
Claim 15
Independent Claim
298 words
A method of forming a portion of a memory cell of a semiconductor integrated circuit; comprising the steps of: etching a substrate to form a first and a second pillar; forming a first and a second surrounding gate transistor adjacent to and within the first and second pillars and the substrate, wherein each transistor has a gate electrode and a source and drain regions, and wherein the gate electrode of the first surrounding gate transistor is adjacent to the first pillar and the source and drain regions of the first surrounding gate transistor are within the first pillar and the substrate, and wherein the gate electrode of the second surrounding gate transistor is adjacent to the second pillar and the source and drain regions of the second surrounding gate transistor are within the second pillar and the substrate; forming a first and a second interconnect, wherein the first interconnect is formed over the first pillar and second gate electrode and the second interconnect is formed over the second pillar and first gate electrode; forming a first and a second pass transistor, wherein each pass transistor has a gate electrode and a source and drain regions, and wherein the source and drain regions of the first pass transistor are formed over the first interconnect and one of the source and drain regions of the second pass transistor are formed over the second interconnect; and forming a first and a second resistive load device wherein the first resistive load device is formed over one of the source and drain regions of the first pass transistor which is formed over the first interconnect and the second resistive load device is formed over one of the source and drain regions of the second pass transistor which is formed over the second interconnect.
Claim 16
Dependent Claim
230 words
A structure consisting of a portion of an integrated circuit device, comprising: a substrate having a plurality of silicon pillars; a first transistor adjacent to and within the pillar and substrate; a first dielectric layer disposed over the integrated circuit having a first and second opening therethrough to expose a portion of the pillar and a portion of a gate of the transistor; a first and a second interconnect disposed over a portion of the first dielectric layer and in the first and second openings; a second dielectric layer disposed over the first dielectric layer and the first and second interconnects, wherein the second dielectric layer has a third opening to expose a portion of the second interconnect; a second transistor disposed over the second dielectric layer and in the third opening; a third dielectric layer disposed over the second transistor, wherein the third dielectric layer has a fourth opening to expose a portion of the second transistor and a fifth opening to expose a portion of the second transistor; a first conductive layer disposed over a portion of the third dielectric layer and in the fourth opening; a fourth dielectric layer disposed over the third dielectric layer and the first conductive layer having a sixth opening to expose the fifth opening; and a second conductive layer disposed over the fourth dielectric layer and in the fifth and sixth openings.
Claim 17
Dependent Claim
17 words
The structure of claim 16 wherein the second transistor comprises a P-type doped source and drain regions.
Claim 18
Dependent Claim
16 words
The structure of claim 16 wherein the first conductive layer comprises an N-type doped polysilicon layer.
Claim 19
Dependent Claim
14 words
The structure of claim 16 wherein the second conductive layer comprises a metal layer.
Claim 20
Dependent Claim
276 words
A structure consisting of a portion of an integrated circuit device, comprising: a first selected supply voltage comprising a substrate having a first and a second pillar; a first and a second surrounding gate transistor wherein the first transistor is adjacent to and within the first pillar and the substrate and the second transistor is adjacent to and within the second pillar and the substrate, wherein each transistor has a conductive path and a control terminal, wherein the first transistor has a conductive path between the first selected supply voltage and an output of a first pass gate, and its control terminal is connected to an output of a second pass gate, and wherein the second transistor has a conductive path between the first selected supply voltage and the output of the second pass gate and a control terminal connected to the output of the first pass gate, and wherein the output of the first pass gate is disposed over the first pillar and the output of the second pass gate is disposed over the second pillar; and a first and a second resistive load device wherein the first resistive load device is connected between the output of the first pass gate and a second selected supply voltage, and wherein the second resistive load device is connected between the output of the second pass gate and the second selected supply voltage, and wherein the first resistive load device is disposed over the source/drain region of the first pass gate disposed over the first pillar and the second resistive load device is disposed over the source/drain region of the second pass gate disposed over the second pillar.
Claim 21
Dependent Claim
233 words
A structure consisting of a portion of an integrated circuit device, comprising: a first transistor disposed over a substrate having a gate electrode and a source and a drain regions; a first dielectric layer disposed over the first transistor having a first and second opening therethrough to expose a portion of the gate electrode and a portion of the one of the source and drain regions; a first and a second interconnect disposed over a portion of the first dielectric layer and in the first and second openings; a second dielectric layer disposed over the first dielectric layer and the first and second interconnects, wherein the second dielectric layer has a third opening to expose a portion of the second interconnect; a second transistor disposed over the second dielectric layer and in the third opening; a third dielectric layer disposed over the second transistor, wherein the third dielectric layer has a fourth opening to expose a portion of the second transistor and a fifth opening to expose a portion of the second transistor; a first conductive layer disposed over a portion of the third dielectric layer and in the fourth opening; a fourth dielectric layer disposed over the third dielectric layer and the first conductive layer having a sixth opening to expose the fifth opening; and a second conductive layer disposed over the fourth dielectric layer and in the fifth and sixth openings.
Claim 22
Dependent Claim
32 words
The method of claim 1, or the structure of claim 21, wherein the first transistor is planar and wherein the source and drain regions of the first transistor are in the substrate.
Claim 23
Dependent Claim
46 words
The structure of claim 21 further comprising: a pillar of silicon substrate extending upward from the substrate, wherein the first transistor is a surrounding gate transistor having a gate electrode adjacent to the pillar and having source and drain regions in the pillar and the substrate.
Claim 24
Dependent Claim
26 words
The method of claim 1, or structure of claim 21, wherein the first transistor comprises an n-channel transistor and the first and second interconnects are N-type.
Claim 25
Dependent Claim
27 words
The method of claim 1, or the structure of claim 21, wherein the first transistor comprises a p-channel transistor and the first and second interconnects are P-type.
Claim 26
Dependent Claim
26 words
The method of claim 1, or the structure of claim 24, wherein the second transistor comprises a p-channel transistor and the first conductive layer is N-type.
Claim 27
Dependent Claim
41 words
The method of claim 1, or the structure or claim 25, wherein the second transistor comprises a p-channel transistor and wherein the first conductive layer comprises a P-type doped upper portion and an N-type doped lower portion in the fourth opening.
Claim 28
Dependent Claim
27 words
The method of claim 1, or the structure of claim 25, wherein the second transistor comprises an n-channel transistor and wherein the first conductive layer is P-type.
Claim 29
Dependent Claim
41 words
A method of claim 1, or the structure of claim 24, wherein the second transistor comprises an n-channel transistor and wherein the first conductive layer comprises an N-type doped upper portion and a P-type doped lower portion in the fourth opening.
References Cited (Backward Citations)
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