EP0585050A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multi-mode frequency synthesiser with reduced jitter
Assignee: Oki Electric Industry Co Ltd
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Filing: 1993-08-19
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Granted: —
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Expires: 2013-08-19
Abstract
Abstract A frequency synthesizer has two cascaded phase-locked loops (48,50), each of which receives an input signal and a feedback signal and generates an output signal. The output of the first phase-locked loop (48) is supplied as input to the second phase-locked loop (50). The output of the second phase-locked loop is supplied as feedback to both the first and second phase-locked loops. The output frequency of the second phase-locked loop is selected by means of programmable frequency dividers (28,30,38,40) inserted in the input and feedback lines of the first phase-locked loop. Such a frequency synthesizer may be used in a television receiver that converts a high-definition television signal (HDTV signal) to a standard television signal for display on a standard size television screen.
Inventors
- 👤 Shosaku c/o Oki Electric Ind. Co. Ltd Tsukagoshi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:21
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/22; H03L7/23; H03L7/235
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
78 words
A frequency synthesizer, comprising: a first phase-locked loop for receiving an input clock signal and a first feedback signal and generating an internal clock signal; and a second phase-locked loop coupled to receive said internal clock signal and a second feedback signal, and generate an output clock signal; wherein said output clock signal is supplied to both said first phase-locked loop and said second phase-locked loop for use as said first feedback signal and said second feedback signal.
Claim 2
Dependent Claim
23 words
The frequency synthesizer of claim 1, wherein said first phase-locked loop has a first programmable frequency divider for dividing said input clock signal.
Claim 3
Dependent Claim
23 words
The frequency synthesizer of claim 1, wherein said first phase-locked loop has a second programmable frequency divider for dividing said first feedback signal.
Claim 4
Dependent Claim
16 words
The frequency synthesizer of claim 1, wherein said first phase-locked loop has a voltage-controlled crystal oscillator.
Claim 5
Dependent Claim
23 words
The frequency synthesizer or claim 1, wherein said second phase-locked loop has a third programmable frequency divider for dividing said internal clock signal.
Claim 6
Dependent Claim
23 words
The frequency synthesizer or claim 1, wherein said second phase-locked loop has a fourth programmable frequency divider for dividing said second feedback signal.
Claim 7
Dependent Claim
15 words
The frequency synthesizer of claim 1, wherein said second phase-locked loop has a voltage-controlled multivibrator.
Claim 8
Dependent Claim
24 words
The frequency synthesizer of claim 1, wherein said first phase-locked loop and said second phase-locked loop are both fabricated in a single integrated circuit.
Claim 9
Dependent Claim
193 words
A frequency synthesizer for receiving an input clock signal and a mode control signal, and generating an output clock signal having a frequency responsive to said mode control signal, comprising: a first frequency divider for dividing said input clock signal by a factor responsive to said mode control signal; a second frequency divider for dividing said output clock signal by a factor responsive to said mode control signal; a first phase comparator coupled to compare outputs of said first frequency divider and said second frequency divider and generate a first error voltage; a first low-pass filter coupled to remove high-frequency components from said first error voltage; a first voltage-controlled oscillator coupled to said first low-pass filter, for generating an internal clock signal with a frequency responsive to said first error voltage; a second phase comparator coupled to compare said internal clock signal with said output clock signal and generate a second error voltage; a second low-pass filter coupled to remove high-frequency components from said second error voltage; and a second voltage-controlled oscillator coupled to said second low-pass filter, for generating said output clock signal at a frequency responsive to said second error voltage.
Claim 10
Dependent Claim
15 words
The frequency divider of claim 9, wherein said first low-pass filter is an RC filter.
Claim 11
Dependent Claim
15 words
The frequency divider of claim 9, wherein said second low-pass filter is an RC filter.
Claim 12
Dependent Claim
16 words
The frequency divider of claim 9, wherein said first voltage-controlled oscillator is a voltage-controlled crystal oscillator.
Claim 13
Dependent Claim
72 words
The frequency divider of claim 9, further comprising: a third frequency divider coupled between said first voltage-controlled oscillator and said second phase comparator, for dividing said internal clock signal by a factor responsive to said mode control signal; and a fourth frequency divider coupled to divide said output clock signal by a factor responsive to said mode control signal prior to input of said output clock signal to said second phase comparator.
References Cited (Backward Citations)
No citation records indexed.
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