Synchronization signal detector, synchronization signal detecting method and demodulator

Claim 2

A synchronization signal detector as claimed in claim 1, wherein each of the two patterns comprises a combination of bit counts not present in the encoded data, bit lengths representing clocks counted between extracted edges in the synchronization signals, each bit count being less than or equal to Tmax, which is the maximum number of clocks between extracted edges in the coded data, and greater than or equal to Tmin, which is the minimum number of clocks between extracted edges in the coded data, inclusive, the patterns also satisfying at least one of the following conditions (i) to (iii): (i) the patterns are each a combination of bit lengths smaller than a maximum number of bit counts between transitions of magnetization of the conversion code; (ii) the patterns are each a combination of different bit counts inclusive of Tmax; and (iii) the patterns are each a combination of Tmax and another Tmax contiguous thereto.

Claim 3

A synchronization signal detector as claimed in claim 1, wherein a modulation code used for encoding the encoded data is a variable length code having different code word lengths depending on input data word lengths, the variable length code being in the format of (d, k; m, n; r), where d, k means a constraint imposed on a train of the same symbol information (d means a minimum length of a symbol "0", k means a maximum length of the symbol "0"), m means a basic data length, n means a basic code length, and r means a basic data length of conversion (constraint length), and d, k, m, n, r, Tmax and Tmin have the following values: d = 4; k = 22; m = 2; n = 5; r = 5; Tmax = 23T and Tmin = 5T.

Claim 4

A synchronization signal detector as claimed in claim 3, wherein a spacing between transitions in each of the two patterns comprises one of the following: 22 bits followed by 22 bits, 23 bits followed by 21 bits, 21 bits followed by 23 bits, 23 bits followed by 22 bits, 22 bits followed by 23 bits, and 23 bits followed by 23 bits.

Claim 5

A synchronization signal detector as claimed in claim 1, wherein a margin bit for tail adjustment is appended to each pattern.

Claim 6

A synchronization signal detector as claimed in claim 5, wherein a total number of bits of the pattern of each of the synchronization signals, including the appended margin bit, is equal to a multiple of five.

Claim 7

A demodulating device for demodulating variable length code data comprising: a synchronization signal detector (22) comprising means (2) for extracting edges of radio frequency (RF) signals detected as binary-valued signals; counting means (6) for counting a number of channel clocks generated by an external source between adjacent extracted edges; holding means (5) for holding a count of the channel clocks previously counted by the counting means while the counting means counts a current number of channel clocks between adjacent extracted edges; detecting means (7,8, 9, 10, 11, 12, 13) for receiving outputs of the counting means (6) and the holding means (5) and detecting synchronization signals by comparing the outputs of the counting means (6) and the holding means (5) with synchronization signals comprising two patterns, one pattern representing a frame synchronization signal and the other pattern representing a synchronization signal for at least error correction; timing controlling means (23) for detecting a block boundary of variable length code data based on synchronization signals detected by the detecting means and for outputting timing control information; code length detection means (24) for detecting a code length of the variable length data; data demodulating means (25) supplied with the detected code length of the variable length data for demodulating the variable length code data into original data in accordance with a demodulation table used to decode the variable length encoded data, based on a detected code length data outputted by the code length detection means and timing control information output by the timing controlling means; and matching means (26) for receiving as inputs demodulated original data output by the data demodulating means and the timing control information output by the timing controlling means and using the inputs for matching the original data to an external circuit.

Claim 9

A synchronization signal detecting method as claimed in claim 8, wherein each of the two patterns comprises a combination of bit counts not present in the encoded data, bit lengths representing clocks counted between extracted edges in the synchronization signals, each bit count being less than or equal to Tmax, which is the maximum number of clocks between extracted edges in the coded data, and greater than or equal to Tmin, which is the minimum number of clocks between extracted edges in the coded data, inclusive, the patterns also satisfying at least one of the following conditions (i) to (iii): (i) the patterns are each a combination of bit lengths smaller than a maximum number of bit counts between transitions of magnetization of the conversion code; (ii) the patterns are each a combination of different bit counts inclusive of Tmax; and (iii) the patterns are each a combination of Tmax and another Tmax contiguous thereto.

Claim 10

A synchronization signal detecting method as claimed in claim 8 wherein a modulation code used for encoding the encoded data is a variable length code having different code word lengths depending on input data word lengths, the variable length code being in the format of (d, k; m, n; r), where d, k means a constraint imposed on a train of the same symbol information (d means a minimum length of a symbol "0", k means a maximum length of the symbol "0"), m means a basic data length, n means a basic code length, and r means a basic data length of conversion (constraint length), and d, k, m, n, r, Tmax and Tmin have the following values: d = 4; k = 22; m = 2; n = 5; r = 5; Tmax = 23T and Tmin = 5T.

Claim 11

A synchronization signal detecting method as claimed in claim 10 wherein a spacing between transitions in each of the two patterns comprises one of the following: 22 bits followed by 22 bits, 23 bits followed by 21 bits, 21 bits followed by 23 bits, 23 bits followed by 22 bits, 22 bits followed by 23 bits, and 23 bits followed by 23 bits.

Claim 12

A synchronization signal detecting method as claimed in claim 8 wherein a margin bit for tail adjustment is appended to each pattern.

Claim 13

A synchronization signal detecting method as claimed in claim 12 wherein a total number of bits of the pattern of each of the synchronization signals, including the appended margin bit, is equal to a multiple of five.

Claim 14

A synchronization signal detector for detecting synchronization signals embedded in radio frequency (RF) signals containing data encoded according to a modulation table, the synchronization signal detector comprising: means (2) for extracting edges of the RF signals detected as binary-valued signals, counting means (6) for counting a number of channel clocks generated by an external channel clock generator between adjacent extracted edges, holding means (5) for holding a count of the channel clocks previously counted by the counting means while the counting means counts a current number of channel clocks generated between adjacent extracted edges, means (7, 8, 9, 10, 11, 12, 13) for receiving outputs of the counting means and the holding means and for detecting synchronization signals by comparing the outputs of the counting means and the holding means with synchronization signals comprising two patterns, one pattern representing a frame synchronization signal and the other pattern representing a synchronization signal for at least error correction, wherein the spacing between transitions in each of the two patterns comprises one of the following: 22 bits followed by 22 bits, 23 bits followed by 21 bits, 21 bits followed by 23 bits, 23 bits followed by 22 bits, 22 bits followed by 23 bits, 23 bits followed by 23 bits, and wherein a margin bit for tail adjustment is appended to each pattern.