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EP0577329A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks

Assignee: AT&T Inc
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Filing: 1993-06-24
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Granted: —
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Expires: 2013-06-24
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Abstract

Abstract Complications of timing recovery in an ATM receiver (200) are overcome by employing a first phase lock loop (208) including a phase comparator (210), filter (211), voltage controlled oscillator (212) and output counter (214) to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter (214) is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then. so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Underflow of the receiver data buffers (202,205) is alleviated by the addition of a "jitter-delay (D j )" value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained (217) by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The stability of the video decoder (204) timing is enhanced by employing an additional phase locked loop in a video display control (203) which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frquency in which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.

Inventors

  • 👤 Barin Geoffry Haskell
  • 👤 Amy Ruth Reibman

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 21:40
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/4302; H04N21/4305; H04N21/4307; H04N21/43072; H04N21/44; H04N21/44004; H04N21/60; H04N21/63; H04N21/643; H04N21/64307; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5614; H04L2012/5616; H04L2012/5638; H04L2012/5646

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 55 words
Apparatus for recovering timing in a receiver comprising: means for obtaining a timing reference signal (SCR) from an asynchronously received signal; phase locked loop means for locking to said obtained timing reference signal; and means for setting an output of said phase locked loop means to a value of an initial obtained timing reference signal.
Claim 2
Dependent Claim 31 words
The apparatus as defined in claim 1 wherein said phase locked loop means includes a counter which is set to said value of said initial obtained reference signal at start up.
Claim 3
Dependent Claim 50 words
The apparatus as defined in claim 1 wherein said output of said phase locked loop means is representative of a value of a system timing clock signal (STC) and further including means for algebraically combining a prescribed jitter delay (D j ) value with said system timing clock signal value.
Claim 4
Dependent Claim 17 words
The apparatus as defined in claim 3 further including means for dynamically generating said jitter delay value.
Claim 5
Dependent Claim 47 words
The apparatus as defined in claim 4 wherein said means for dynamically generating said jitter delay value is responsive to a fullness value of a data buffer in the receiver and an error signal from said phase locked loop means for dynamically generating said jitter delay value.
Claim 6
Dependent Claim 42 words
The apparatus as defined in claim 5 wherein said means for algebraically combining includes means for subtracting said jitter delay value from said system timing clock signal value to obtain a modified representation of said system timing clock signal (STC-D j ).
Claim 7
Dependent Claim 30 words
The apparatus as defined in claim 6 wherein said modified representation of said system timing clock signal is utilized to control displaying video information received in said asynchronously received signal.
Claim 8
Dependent Claim 31 words
The apparatus as defined in claim 7 wherein said modified representation of said system timing clock signal is further utilized to control displaying audio information received in said asynchronously received signal.
Claim 9
Dependent Claim 32 words
The apparatus as defined in claim 8 wherein the receiver includes a video data buffer in said fullness representation is of the amount of video data stored in said video data buffer.
Claim 10
Dependent Claim 33 words
The apparatus as defined in claim 9 wherein the receiver further includes video display control means for controlling supplying video data presentation units stored in said video data buffer to a video decoder.
Claim 11
Dependent Claim 38 words
The apparatus as defined in claim 10 wherein the receiver further includes an audio data buffer and video display control means for controlling supplying video data representation units stored in said audio data buffer to an audio decoder.
Claim 12
Dependent Claim 54 words
The apparatus as defined in claim 11 wherein said video display control means is responsive to said modified representation of said system timing clock signal and to prescribed time stamp values received with said video data in said asynchronouslsy received signal for controlling the supplying of said video representation units to said video decoder.
Claim 13
Dependent Claim 54 words
The apparatus as defined in claim 12 wherein said audio display control means is responsive to said modified representation of said system timing clock signal and to prescribed time stamp values received with said audio data in said asynchronously received signal for controlling the supplying of said audio represtation units to said audio decoder.
Claim 14
Dependent Claim 34 words
The apparatus as defined in claim 12 wherein said video display control means includes time based corrector means for enhancing the transmissiosn timing of said video representation units being supplied to said video decoder.
Claim 15
Dependent Claim 55 words
The apparatus as defined in claim 14 wherein said time based corrector means includes second phase locked loop means responsive to a control signal representative of an algebraic combination of said modified system timing clock signal and a decoding time stamp value corresponding to the video presentation unit to be supplied to said video decoder.

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