EP0577115A2
Expired / Lapsed
EP
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Programmed I/O Ethernet adapter with early interrupts for accelerating data transfer
Assignee: 3Com Corp
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Filing: 1993-06-30
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Granted: —
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Expires: 2013-06-30
Abstract
Abstract In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
Inventors
- 👤 Richard S. Reid
- 👤 Richard Hausman
- 👤 Paul William Sherer
- 👤 James P. Rivers
- 👤 Cynthia Zikmund
- 👤 Glenn W. Connery
- 👤 Niles E. Strohl
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:02
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9063; H04L49/9068; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; H04L12/00; H04L12/28; H04L12/40; H04L12/40006; H04L12/40013; H04L12/407; H04L12/413; H04L49/901; H04L49/9031; H04L49/9078; H04L12/40032
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
172 words
A data communications adapter apparatus for coupling a host computer to a computer network employing communications media, the adapter comprising: a) a transceiver coupled to receive and transmit data over the media; b) a transmit data buffer; c) data transmit control circuitry coupled to said transceiver, to said transmit data buffer, and to said host computer, for generating a packet transmit signal causing said transceiver to begin transmitting data from said transmit data buffer over said communications media; d) a receive data buffer; and e) data receive control circuitry coupled to said transceiver, to said receive data buffer, and to said host computer, for storing data received by said transceiver in said receive data buffer, and for generating a receive interrupt signalling to said host computer that data has been received by said transceiver, wherein said data receive control circuitry is operative to generate a receive interrupt once said transceiver has received over said communications media a predetermined number of bytes of a data packet less than all of said data packet.
Claim 2
Dependent Claim
55 words
The adapter of claim 1, further comprising: a) ethernet control circuitry; and b) host interface circuitry, wherein said ethernet control circuitry, said host interface circuitry, said data receive control circuitry, said data transmit control circuitry, said receive data buffer and said transmit data buffer are all contained in a single Application Specific Integrated Circuit (ASIC).
Claim 3
Dependent Claim
13 words
The adapter of claim 1, wherein said data receive control circuitry is programmable.
Claim 4
Dependent Claim
41 words
The adapter of claim 1, wherein said data transmit control circuitry is programmable to generate said packet transmit signal when said transmit data buffer contains a predetermined number of bytes of a data packet less than all of said data packet.
Claim 5
Independent Claim
92 words
A method of transferring a packet of data from a computer network communications media through an adapter to a host computer, said method comprising the steps of: a) receiving from said communications media through a transceiver and storing in an adapter receive buffer a predetermined first receive threshold number of bytes of said packet; b) thereupon generating a first early receive interrupt from said adapter to said host computer; and c) thereafter receiving from said communications media through said transceiver and storing in said adapter receive buffer a remainder of said packet.
Claim 6
Dependent Claim
48 words
The method of claim 5, wherein said host computer employs a driver allowing for early indications and having an early lookahead size, and wherein step of receiving a predetermined first receive threshold number of bytes comprises receiving a number of bytes substantially equal to said early lookahead size.
Claim 7
Dependent Claim
117 words
The method of claim 5, wherein said host computer employs a driver allowing for early indications and having an early lookahead size, wherein said adapter and said host computer together have an interrupt latency time, said method further comprising after said step of receiving a predetermined first receive threshold number of bytes, the step of continuing to receive from said communications media through said transceiver and store in an adapter receive buffer bytes of said packet, wherein said step of receiving a predetermined first receive threshold number of bytes comprises receiving a predetermined first receive threshold number of bytes substantially equal to said early lookahead size less a predetermined data receive rate times said interrupt latency time.
Claim 8
Dependent Claim
50 words
The method of claim 7, further comprising, after the step of generating said first interrupt, the steps of a) evaluating the number of bytes stored in said adapter receive buffer against said early lookahead size; and b) adjusting said receive threshold if said evaluating step does not indicate substantial equality.
Claim 9
Dependent Claim
104 words
The method of claim 5, wherein said packet comprises a preamble specifying a length of said packet in bytes, said method further comprising after said step of generating a first early receive interrupt and before said step of receiving a remainder of said packet, the steps of: a) adjusting said receive threshold according to said length of said packet; b) continuing to receive from said communications media through said transceiver and store in an adapter receive buffer bytes of said packet; and c) thereafter generating a second early receive interrupt from said adapter to said host computer, prior to complete reception of said packet.
Claim 10
Dependent Claim
129 words
The method of claim 5, wherein said adapter receive buffer has a predetermined size, said method further comprising the steps of: a) if additional bytes of a data packet are received from said communications media through said transceiver and stored in said adapter receive buffer while said adapter receive buffer contains allotted bytes of at least one packet not yet completely transferred to said host computer, such that the total number of allotted bytes in said adapter receive buffer is equal to said size of said adapter receive buffer less a predetermined adapter receive buffer free byte threshold, initiating a direct memory access (DMA) mode; and b) receiving from said communications media through said transceiver and storing in a host computer receive buffer through DMA additional bytes of data.
Claim 11
Independent Claim
113 words
A method of transferring a packet of data from a host computer through an adapter to a computer network communications media, said method comprising the steps of: a) transferring from said host computer and storing in an adapter transmit buffer an early transmit threshold number of bytes of said packet; b) thereupon initiating transmission of said packet through said transceiver from said adapter transmit buffer to said computer network communications media; and c) receiving from said host computer and storing in said adapter receive buffer a remainder of said packet, at least partially in parallel with transmitting said packet through said transceiver from said adapter transmit buffer to said computer network communications media.
Claim 12
Independent Claim
180 words
A method of transferring through an adapter packets of data between a host computer and a computer network communications media, said method comprising the steps of: a) receiving from said communications media through said transceiver and storing in an adapter receive buffer a predetermined first receive threshold number of bytes of a first packet; b) thereupon generating a first early receive interrupt from said adapter to said host computer; c) receiving from said communications media through said transceiver and storing in said adapter receive buffer a remainder of said first packet; d) transferring from said host computer and storing in an adapter transmit buffer an early transmit threshold number of bytes of a second packet; e) thereupon initiating transmission of said second packet through said transceiver from said adapter transmit buffer to said computer network communications media; f) receiving from said host computer and storing in said adapter receive buffer a remainder of said second packet, at least partially in parallel with transmitting said second packet through said transceiver from said adapter transmit buffer to said computer network communications media.
Claim 13
Dependent Claim
108 words
The method of claim 12, wherein each packet comprises a preamble specifying a length of said each packet in bytes, said method further comprising after said step of generating a first early receive interrupt and before said step of receiving a remainder of said first packet, the steps of: a) adjusting said receive threshold according to said length of said first packet; b) continuing to receive from said communications media through said transceiver and store in an adapter receive buffer bytes of said first packet; and c) generating a second early receive interrupt from said adapter to said host computer prior to complete reception of said first packet.
Claim 14
Dependent Claim
132 words
The method of claim 13, wherein said adapter receive buffer has a predetermined size, said method further comprising the steps of: a) if additional bytes of a data packet are received from said communications media through said transceiver and stored in said adapter receive buffer while said adapter receive buffer contains allotted bytes of at least one packet not yet completely transferred to said host computer, such that the total number of allotted bytes in said adapter receive buffer is equal to said size of said adapter receive buffer less a predetermined adapter receive buffer free byte threshold, initiating a direct memory access (DMA) mode; and b) receiving additional bytes of data from said communications media through said transceiver and storing through DMA said additional bytes in a host computer receive buffer.
Claim 15
Dependent Claim
262 words
An electronic register stack structure for providing, for each of a plurality of actions, a condition represented by a predetermined number of condition flags, wherein said actions may have, upon completion, one of a first condition and at least one alternate condition, wherein a condition of one action at a time is currently accessible from said register stack structure, wherein the currently accessible condition may be removed from said register stack structure so as to make accessible a condition of a remaining action by popping said register stack structure, wherein storing conditions of said actions is halted upon an action having one of said at least one alternate condition, said register stack structure comprising: a) a condition register comprising said predetermined number of condition flags; b) a counter register; c) means for storing a condition for a new action to said register stack structure by modifying contents of said condition register as necessary to indicate said condition of said new action and incrementing said counter register, wherein said counter indicates whether said currently accessible condition is to be said condition of said new action or a condition of a remaining action; d) means for providing said currently accessible condition by i) if said counter indicates that said currently accessible condition is to be said condition of said new action, providing contents of said condition register, and ii) if said counter indicates that said currently accessible condition is to be a condition of a remaining action, providing said first condition; and e) means for popping said register stack structure by decrementing said counter.
Claim 16
Dependent Claim
27 words
The register stack structure of claim 15, wherein said first condition is a successful condition and each said at least one alternate condition is an error condition.
Claim 17
Dependent Claim
37 words
The register stack structure of claim 15, wherein said means for providing said currently accessible condition further provides a zero condition when said counter indicates that all action conditions have been popped from said register stack structure.
References Cited (Backward Citations)
EP0290129A2
Cited
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