EP0576150A2
Expired / Lapsed
EP
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Digital serializer and time delay regulator
Assignee: Advanced Micro Devices Inc
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Filing: 1993-05-26
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Granted: —
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Expires: 2013-05-26
Abstract
Abstract A method and apparatus for providing a digitally self calibrating delay element by launching a pulse of 1/2 Tb into a delay line and by determining the position at any instant of said pulse in the delay line and by digitally adjusting the delay of said delay line, and a digital serializer with switches clocked by these pulses.
Inventors
- 👤 Bin Guo
- 👤 Jim Kubinec
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 15:06
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03M; H03M9/00; H04J3/06; H04J3/0635; H04J3/0685
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
231 words
A digitally regulated time delay circuit comprising a plurality of delay units, each said delay unit calibrated to exhibit a time delay T, where T≦ Tb, each delay unit having an input terminal and an output terminal, said delay units being connected in series; means to launch a pulse having a width less than a bit period into said input terminal of one of said plurality of delay units; a phase detector, said phase detector being connected to the output of the last of said delay units, said phase detector comprising, (a) a delay line having a plurality of taps, (b) a registration means, said registration means coupled to the output of a plurality of said delay units and to each of said phase detector taps, said registration means for determining simultaneously on-the-fly the status of each node to which it is connected and for providing an output indicative thereof, and (c) combinatorial and sequential logic means coupled to said registeration means output, said combinatorial and sequential logic means providing an output indicative of said delay status; an up/down controller, said up/down controller being connected to and responsive to said phase detector output, said up/down controller providing an output which is a digital command code for control of said delay units; and wherein each said plurality of delay units is connected to and responsive to said up/down controller digital command code.
Claim 2
Dependent Claim
22 words
The regulated time delay circuit of claim 1 wherein said delay unit comprises a course step unit and a fine step unit.
Claim 3
Dependent Claim
35 words
The delay circuit of step 2 wherein said coarse step unit includes a MUX, said MUX having one input for receiving one output from each of said delay units, said MUX further having one output.
Claim 4
Dependent Claim
38 words
The delay circuit of step 3 wherein one of said MUX inputs is made available at said MUX output and wherein the selection available at said MUX output is responsive to and determined by said digital command code.
Claim 5
Dependent Claim
77 words
The circuit of claim 4 wherein said fine step unit contains more delay units than the number of delay units in said coarse step delay unit and wherein each said delay unit in said fine step unit has an input and output; a second MUX, said second MUX having a sufficient plurality of inputs, one of each of said second MUX inputs being connected to an output of said delay unit of said fine delay step unit.
Claim 6
Dependent Claim
127 words
A digital data serializer for high data rate transmission comprising a first plural stage register for latching a multibit word to be serialized, each said register stage having an output; a gating network, said gating network including a plurality of switches, each said switch including an input, output and control terminal, the output terminal of all the said switches coupled to a node and the input terminal of each said switch connected to a different one of said register stage outputs; a digitally regulated time delay circuit, comprising a plurality of nominal 1/2 Tb delay units, connected in series from their inputs to their outputs; and each control terminal of said gating network switches being connected to a different input of one of said 1/2 Tb units.
Claim 7
Dependent Claim
15 words
The serializer of Claim 6 wherein said node is coupled to a pull up circuit.
Claim 8
Dependent Claim
51 words
The serializer of Claim 7 including means to control the delay in each said 1/2 Tb delay units, said means including an up/down shifter which issues a digital command code responsive to the sensed physical instantaneous location of a transition of a pulse moving through said series 1/2 Tb delay units.
Claim 9
Dependent Claim
85 words
The serializer of Claim 8 wherein said means to control the delay in each said 1/2 Tb delay units further includes, (a) a sampling register, said sampling register having inputs and output, said inputs being connected to a plurality of said 1/2 Tb delay units for storing their status on-the-fly, and (b) combinatorial and sequential logic means connected to the outputs of said sampling register for providing an analysis of said sampling register outputs indicative of the physical location of the pulse in said delay.
Claim 10
Dependent Claim
70 words
An all digital method for regulating a delay line comprising launching a pulse having a pulse width equal to 1/2 Tb into a delay line, including a plurality of serially connected 1/2 Tb delay units; determining the position at any instant of said pulse in said delay line, adjusting said delay of each said 1/2 Tb delay units responsive to the said position of said pulse in said delay line.
Claim 11
Dependent Claim
53 words
The method of claim 10 wherein the step of determining the position at any instant of said pulse includes sampling the output of said plurality of series connected delay elements, and analyzing said sampled output using combinatorial and sequential logic techniques to determine the position of said pulse relative to a reference location.
Claim 12
Dependent Claim
52 words
The method of claim 11 wherein the step of adjusting said delay of each said 1/2 Tb delay units includes generating a digital command code with an up/down shifter responsive to said determination of said pulse position, and controlling the delay of each said delay unit responsive to said digital command code.
References Cited (Backward Citations)
No citation records indexed.
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