EP0575171A2
Expired / Lapsed
EP
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Enhanced system management method and apparatus
Assignee: National Semiconductor Corp
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Filing: 1993-06-17
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Granted: —
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Expires: 2013-06-17
Abstract
Abstract A microprocessor is disclosed which has enhanced system management capabilities. The microprocessor includes circuitry for accessing external memory within a known address space. Circuitry is provided for programmably defining a range of addresses within the address space for use by system management routines. In the preferred embodiment, the system management memory is defined by a starting address and a block size. Further, upon receiving a system management interrupt, the microprocessor stores that processor status information which is always affected upon initiation of a system management routine; other information is stored, such that the time overhead associated with system management routine is minimized. Additional features that provide added functionality are: (a) an NMI ENABLE feature allows servicing NMIs during SMM operations; (b) an SMI LOCK feature prevents unauthorized access to SMM space or SMM routines, such as by hackers or viruses; (C) an I/O buffering feature allows I/O information (operand, size, and port address) facilitates transparent retries of I/O operations that result in a trap to an SMI routine, such as for power-up of peripherals; and (d) a software SMM instruction provides added flexibility in the use of SMM operations.
Inventors
- 👤 Robert D. Maher Iii
- 👤 Raul A. Garibay, Jr.
- 👤 Margaret R. Herubin
- 👤 Mark Warden Hervin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 19:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F1/00; G06F1/24; G06F12/00; G06F12/02; G06F12/0223
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
54 words
A microprocessor, intended in use to be coupled to a memory, which microprocessor has circuitry for programmably defining a range of addresses within a selected address space of the memory for storing system management routines; and circuitry responsive to signals requesting a system management routine, to access the memory within the selected address space.
Claim 2
Dependent Claim
20 words
The microprocessor of claim 1 in combination with a memory, wherein the microprocessor and the memory comprise separate, interconnected devices.
Claim 3
Dependent Claim
17 words
The microprocessor of claim 1 or claim 2 wherein said defining circuitry comprises a plurality of registers.
Claim 4
Dependent Claim
25 words
The microprocessor of claim 2 wherein said plurality of registers comprise one or more registers for storing a starting address for said range of addresses.
Claim 5
Dependent Claim
28 words
The microprocessor of claim 2 or claim 3 wherein said plurality of registers further comprise one or more registers for storing a size for said range of addresses.
Claim 6
Dependent Claim
26 words
The microprocessor of any preceding claim, and further comprising circuitry for programmably storing selected processor status information responsive to a request for a system management routine.
Claim 7
Dependent Claim
68 words
A microprocessor, intended in use to be coupled to a memory, which the microprocessor has circuitry for defining a range of addresses within a selected address space of the memory, for storing system management routines; circuitry responsive to signals requesting a system management routine, to access said selected address space; and circuitry for programmably storing selected processor status information responsive to said signal requesting a system management routine.
Claim 8
Dependent Claim
28 words
The microprocessor of Claim 6 or Claim 7 and further comprising circuitry for automatically storing predetermined processor status information responsive to said request for a system management routine.
Claim 9
Dependent Claim
24 words
The microprocessor of Claim 8 wherein said circuitry for programmably storing comprises circuitry for programmably storing selected processor information to a programmably selected address.
Claim 10
Dependent Claim
21 words
The microprocessor of Claim 7 wherein said circuitry for programmably storing comprises circuitry for programmably storing information associated with selected registers.
Claim 11
Dependent Claim
16 words
The microprocessor of any preceding Claim, and further comprising circuitry for selectively disabling said receiving circuitry.
Claim 12
Dependent Claim
161 words
A computer system including a microprocessor and memory, where the microprocessor can operate in either normal mode or system management mode (SMM), and where the microprocessor operating in normal mode responds to a non-maskable interrupt (NMI) by executing a corresponding NMI handler routine, comprising: circuitry in the microprocessor that defines an SMM address space within a selected address space of the memory for use in executing SMM routines to perform SMM operations; circuitry in the microprocessor that, in response to an SMM interrupt invokes an SMM routine which performs a selected SMM operation and then returns the microprocessor to normal mode operation; and circuitry in the microprocessor for selectively enabling recognition of NMIs during SMM operations, such that, with NMI enabled, an SMM routine will execute the corresponding NMI handler routine, but with NMI not enabled, an SMM routine will not respond to the NMI interrupt, whereby the NMI interrupt can only be serviced after a return to normal mode operation.
Claim 13
Dependent Claim
24 words
The system of Claim 12, wherein the SMM routine automatically stores predetermined microprocessor status information responsive to said request for a system management routine.
Claim 14
Dependent Claim
23 words
The system of Claim 12 or Claim 13, wherein the circuitry that defines SMM address space includes registers programmably storing SMM configuration information.
Claim 15
Dependent Claim
113 words
A computer system including a microprocessor and memory, where the microprocessor can operate in normal mode or system management mode (SMM), comprising: circuitry in the microprocessor that defines SMM configuration information for SMM operations, including an SMM address space within a selected address space of the memory for use in executing SMM routines to perform SMM operations; circuitry in the microprocessor that, in response to an SMM signal invokes an SMM routine which performs a selected SMM operation and then returns the microprocessor to normal mode operation; and circuitry in the microprocessor that, when an SMM lock state is enabled, prevents any activity other than an SMM routine from modifying SMM configuration information.
Claim 16
Dependent Claim
28 words
The system of Claim 15, wherein, once SMM lock is enabled, it remains enabled until power-down of the microprocessor unless SMM lock is disabled by an SMM routine.
Claim 17
Dependent Claim
124 words
A computer system including a microprocessor and memory, where the microprocessor can operate in normal mode or system management mode (SMM), comprising: circuitry in the microprocessor that, during normal mode operations, stores I/O information about a current I/O operation in a temporary register; circuitry in the microprocessor that defines an SMM address space within a selected address space of the memory for use in executing SMM routines to perform SMM operations; and circuitry in the microprocessor that, in response to an SMM signal, invokes an SMM routine which performs a selected SMM operation including storing selected microprocessor status information within the SMM address space, and then returns the microprocessor to normal mode operation; the microprocessor status information including I/O information from the temporary register.
Claim 18
Dependent Claim
22 words
The system of Claim 17, wherein the I/O information comprises the associated operand, operand size, and port address for the I/O operation.
Claim 19
Dependent Claim
63 words
The system of Claim 17 or Claim 18, wherein, during an SMM operation initiated because of the powered-down state of a peripheral to which the microprocessor operating in normal mode was attempting to write data, the associated current I/O information stored in SMM space is interrogated and then used to retry the I/O operation during normal operations after the peripheral is powered up.
Claim 20
Dependent Claim
112 words
A computer system including a microprocessor and memory, where the microprocessor can operate in normal mode or system management mode (SMM), comprising: circuitry in the microprocessor that defines an SMM range of addresses within a selected address space of the memory for use in executing SMM routines to perform SMM operations; and circuitry in the microprocessor that, in response to either (i) an SMM signal external to the microprocessor, or (ii) an SMM signal provided by software being executed by the microprocessor during normal mode operations, invokes an SMM routine which performs a selected SMM operation including programmably storing selected processor status information, and then returns the microprocessor to normal mode operation.
Claim 21
Dependent Claim
31 words
The system of Claim 20, wherein an SMM routine selectively stores microprocessor status information within the SMM address space, including an indication of whether the SMM operation was initiated by software.
References Cited (Backward Citations)
No citation records indexed.
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