EP0570950A2
Expired / Lapsed
EP
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Advanced parallel array processor (APAP)
Assignee: International Business Machines Corp
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Filing: 1993-05-19
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Granted: —
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Expires: 2013-05-19
Abstract
Abstract A parallel array processor is formed. Eight processors on a single chip have their own associated processing element, memory, and I/O and are interconnected with a hypercube based topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The new architecture merges processor and memory with multiple PMEs in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor.
Inventors
- 👤 Thomas Norman Barker
- 👤 Clive Allan Collins
- 👤 Michael Charles Dapp
- 👤 James Warren Dieffenderfer
- 👤 Donald George Grice
- 👤 Peter Michael Kogge
- 👤 David Christopher Kuchinski
- 👤 Billy Jack Knowles
- 👤 Donald Michael Lesmeister
- 👤 Richard Ernest Miles
- 👤 Richard Edward Nier
- 👤 Erie Eugene Retter
- 👤 Robert Reist Richardson
- 👤 David Bruce Rolfe
- 👤 Nicholas Jerome Schoonover
- 👤 Vincent John Smoral
- 👤 James Robert Stupp
- 👤 Paul Amba Wilkinson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 21:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F15/803; G06F15/8053; G06F15/8092; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30181; G06F9/30189; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3851; G06F9/3885; G06F9/3887; G06F9/3889; G06F9/3891; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
50 words
A computer system, comprising: a plurality of processor memory elements on a common substrate, each of said processor memory elements having internal and external communications paths for communication between a plurality of other processor memory elements on the substrate and for communication with other processing elements external to said substrate.
Claim 2
Dependent Claim
49 words
A computer system according to claim 1 wherein a node of a processor array has multiple single processor elements comprising a a network node of eight or more processors with their associated memory with fully distributed I/O routers and signal I/O ports at each of the single processor elements.
Claim 3
Dependent Claim
36 words
A computer system according to claim 1 wherein a node processing memory element has internal data flows using high speed hard registers to feed distributed ALU and and I/O router registers and logic for all operations.
Claim 4
Dependent Claim
51 words
A computer system according to claim 1 wherein a node has multiple processor memory elements and is connected to other nodes in a cluster network with data routing distributed between hardware and software, with hardware provided for performing inner loop transfers and minimizing overhead on the outer loops of the node.
Claim 5
Dependent Claim
39 words
A computer system according to claim 1 further comprising means for enabling distributed fault tolerance by an n-redundancy mode, where the need of the data is given a redundancy number and replicated within an array of processing memory elements.
Claim 6
Dependent Claim
54 words
A computer system according to claim 1 further comprising within a processor memory element: a native instruction set, means for providing an expandable multiply function, a programmer router for routing information alternatively left/right, NEWS matrix, NEWS/up-down, hypercube, and wherein said programmable router is employs a hardwired distributed router provided by each processing memory element.
Claim 7
Dependent Claim
35 words
A computer system according to claim 1 wherein each computer element (PME) has 2n processors, memory and routers within a single chip and internal and external communication paths which minimize delays due to chip crossings.
Claim 8
Dependent Claim
85 words
A computer system according to claim 1 wherein the common substrate is a chip and eight processing memory elements are provided on said chip, said chip providing a node of system composed of a plurality of computer systems, and wherein processor memory elements within the node are connected in a binary hypercube communication network, and each node has eight processing memory elements on said chip, and communication between processing memory elements is controlled by in and out registers under control of each of processing elements.
Claim 9
Dependent Claim
51 words
A computer system according to claim 1 further comprising a system controller, and a broadcast control interface, said broadcast control interface enabling the controller and the processor memory elements to interrogate a processor memory element for status information within the processor memory element even during operation of said processor memory element.
Claim 10
Dependent Claim
42 words
A computer system according to claim 1 further comprising a system controller, and a broadcast control interface, said broadcast control interface providing means for providing inter-processor busing protocols, said system controller functioning as an array controller for nodes of processing memory elements.
Claim 11
Dependent Claim
17 words
A computer system according to claim 1 wherein one of two communication modes permits direct memory addressing.
Claim 12
Dependent Claim
57 words
A computer system according to claim 1 organized as a massively parallel machine with nodes interconnected as a n dimensional network cluster with parallel communication paths between processor memory elements along said internal and external communication paths providing a processing array, and further comprising an array controller such that varying size systems can be configured by replication.
Claim 13
Dependent Claim
43 words
A computer system according to claim 1 organized as an n-dimensional network of processing memory elements having the capability to perform MIMD operations and wherein an array of nodes is provided with means for data packing/unpacking for high speed pipelined floating point operations.
Claim 14
Dependent Claim
36 words
A computer system according to claim 1 wherein a node has multiple processor memory elements on a chip with interconnections to their immediate neighbors with an interconnection pattern that results in a three dimensional cube structure.
Claim 15
Dependent Claim
35 words
A computer system according to claim 1 wherein a node has multiple processor memory elements coupled by an optical path and an on-chip optical driver/receiver for coupling of nodes in an array of 4d toruses.
Claim 16
Dependent Claim
39 words
A computer system according to claim 1 including an array director having: a. an application processor interface, b. a cluster synchronizer, c. a cluster controller for an array of nodes, and d. a fast I/O for a zipper connection.
Claim 17
Dependent Claim
180 words
A computer system, comprising: a control unit, an interconnection system and a processing array for parallel processing having nodes which are interconnected with the distribution system to other processing nodes, wherein: the control unit is programmable and has means for enabling the processing array having an array of processing elements to operate in coordination and which also can enable a system control program to operate subsets of the parallel array with each subset dedicated to different applications or different phases of a single application program's processing, the interconnection system provides physical connections between the control unit and the elements of the parallel array of processing elements enabling data and control transfers which are completely independent of the transfer of data between elements of the processing array, the interconnection system distributes functions associated with data transfer between elements of the processing array and distributed functions to be embedded in processing node software, a processing array provides non-shared memory and compute services and which can be partitioned to meet the needs of applications and system needs, and the processing array is scalable.
Claim 18
Dependent Claim
43 words
The computer system of Claim 17 wherein applications can be processed that perform the serial portions of an application task within the controller or within a single element of the processing array, while distributing the parallel portions of the task among processing elements.
Claim 19
Dependent Claim
62 words
The computer system of Claim 17 wherein the control unit provides the services needed to operate the parallel processing array in either SIMD or MIMD modes, and which also provides the capability to switch between the two modes on and instruction-by-instruction basis or on a block-of-instructions by block-of-instructions basis where a block of instructions is any size determined by a control program.
Claim 20
Dependent Claim
49 words
The computer system of Claim 17 applications can be processed that perform the serial portions of an application task in a SIMIMD mode and wherein a a single element can source a broadcast bus of the processing array, while distributing the parallel portions of the task among processing elements.
References Cited (Backward Citations)
US4975834A
Cited
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