EP0570741A2
Expired / Lapsed
EP
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Controller for a SIMD/MIMD processor array
Assignee: International Business Machines Corp
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Filing: 1993-04-30
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Granted: —
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Expires: 2013-04-30
Abstract
Abstract A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller. A SIMD processor can be efficiently used by (a) keeping maximun number of elements working on the problem, (b) feeding the array a continuous stream of commands with pipeline construction and looping control ahead of time outside the array, and (c) efficient problem implementation by hierarchical breakdown of the problem.
Inventors
- 👤 Paul Amba Wilkinson
- 👤 Thomas Norman Barker
- 👤 James Warren Dieffenderfer
- 👤 Peter Michael Kogge
- 👤 Donald Michael Lesmeister
- 👤 Robert Reist Richardson
- 👤 Vincent John Smoral
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30145; G06F9/3017; G06F9/3885; G06F9/3887; G06F9/3889
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
89 words
A Controller for a computer system capable of processing SIMD with an array of processors which can execute data in parallel, comprising a plurality of array processing elements which are coupled for intercommunication of data and instructions as pickets, each picket having plural mechanisms which permit each picket to have a variety of execution capabilities to permit a variety of modes to be obtained for executionof data within a picket and enabling interpretation of SIMD commands within the picket, such combined mode of operation called and identified herein SIMIMD.
Claim 2
Dependent Claim
25 words
A SIMIMD array processor controller according to Claim 1 which controls the array of processor elements using multiple stages of control with a hierarchial structure.
Claim 3
Dependent Claim
14 words
A SIMIMD array processor controller according to Claim 2 with three stages of control.
Claim 4
Dependent Claim
42 words
A SIMIMD array processor controller according to Claim 2 in which the lowest level of hierarchical control consists of an array microcontroller which directly controls the array of processing elements by feeding it a string of commands, addresses, indexes, and/or counter values.
Claim 5
Dependent Claim
35 words
A SIMIMD array processor controller according to Claim 2 in which an intermediate level of hierarchical control consists of an instruction sequencer that interprets instructions and feeds commands to select sequences in the array microcontroller.
Claim 6
Dependent Claim
41 words
A SIMIMD array processor controller according to Claim 2 w a pipeline FIFO file accepts data from the instruction sequencer when they are ready and dispenses them to the microcontroller when the microcontroller is finished with its last string of commands.
Claim 7
Dependent Claim
53 words
A SIMIMD array processor controller according to Claim 2 in which the highest level of hierarchical control consists of a subsystem controller that takes high level commands from a host and builds the highlevel functions using a combination of canned routines in the instruction sequencer and low level commands in the array microcontroller.
Claim 8
Dependent Claim
23 words
A SIMIMD array processor controller according to Claim 2 in which a common command format is shared by plural stages of the controller.
Claim 9
Dependent Claim
40 words
A SIMIMD array processor controller according to Claim 2 in which the SIMD array can be controlled in such a way as to simulate MIMD function by executing instructions within the array elements that may be unique to the elements.
Claim 10
Dependent Claim
33 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 4 which sends SIMD commands, data, addresses, indexes, and counter values simultaneously to all of the Processing Elements of the array.
Claim 11
Dependent Claim
31 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 4 which also sends SIMD commands, data, addresses, indexes, and counter values to a Local Store within the Controller.
Claim 12
Dependent Claim
51 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 10 which sends SIMD commands, data, addresses, indexes, and counter values to all of the pickets and local store with a common clock such that each picket recieves the same command on the same cycle of a control clock.
Claim 13
Dependent Claim
32 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 10 which commands sent to all pickets, supply the microorders that control the ALU, Muxes, and regs in each picket.
Claim 14
Dependent Claim
49 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 13 which microorders may also control hardware that allows each picket to vary the effect of the command in a way to do something different than an other picket is doing with the same command (Local Autonomy).
Claim 15
Dependent Claim
29 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 10 which holds SIMD commands, data, addresses, indexes, and counter values in a memory as microcontrol words.
Claim 16
Dependent Claim
43 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 15 which holds SIMD commands, data, addresses, indexes, and counter values in memory in linear strings of commands that are sent to the array of processors to be executed in sequence.
Claim 17
Dependent Claim
26 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 16 which linear strings of commands are identified and invoked by their beginning addresses.
Claim 18
Dependent Claim
32 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 17 which requests and receives the next beginning address from a FIFO fed by the prior stage of the controller.
Claim 19
Dependent Claim
34 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 11 which maintains active addresses, indexes, and counter values in a local regs file with storage capacity sufficient to support many functions.
Claim 20
Dependent Claim
36 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 11 which computes/increments/decrements values of addresses, indexes, and counter values located in local regs via adder and data flow facilities dedicated to that function.
Claim 21
Dependent Claim
30 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 11 which sends addresses, counter values, and other incremented or decremented values to the array of processors simultaneously.
Claim 22
Dependent Claim
38 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 10 which monitors all of the processors in the array of processors and provides Status of the array to next prior stage of the array controller.
Claim 23
Dependent Claim
29 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 22 which obtains status through a set of signal lines common to all of the array processors.
Claim 24
Dependent Claim
42 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 22 which obtains status through a set of signal lines such that each of the pickets who has a specific condition drives one of the lines to the active state.
Claim 25
Dependent Claim
37 words
A SIMIMD array processor controller with a MICROCONTROL stage according to Claim 22 which obtains status through a set of signal lines that are latched in the controller. This status collection system is called the STATUS FUNNEL.
Claim 26
Dependent Claim
36 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 5 which generates and sequences commands for the array microcontrol stage and puts them in a FIFO for eventual use by the microcontrol stage.
Claim 27
Dependent Claim
36 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 5 which effectively segregates the sequence and looping control of the problem being executed from the actual manipulation of data in the processor array.
Claim 28
Dependent Claim
27 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 26 which sequences of commands are starting addesses for linear sequences in the Microcontrol stage.
Claim 29
Dependent Claim
29 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 27 which looping control and decision making control functions are implemented within the sequencer in hardwired logic.
Claim 30
Dependent Claim
44 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 29 which looping and decision making instructions include: GOSUB - RETURN IF - THEN - ELSE DO - NEXT DO IMMEDIATE - NEXT DO - NEXT IF START MICROCONTROL SEGMENT AT X.
Claim 31
Dependent Claim
26 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 29 which includes a set of registers that contain Iteration counts and Nesting Control.
Claim 32
Dependent Claim
35 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 27 which contains a set of programs or routines in a memory within the sequencer. The set of routines is called Canned Routines.
Claim 33
Dependent Claim
28 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 32 which canned routines can include functions to do: Floating Point Add, Matrix Multiply, Sin(x), etc.
Claim 34
Dependent Claim
39 words
A SIMIMD array processor controller with a SEQUENCER stage according to Claim 26 which has instructions that interpret the array status from the microcontroller or pass the status to the next higher level of control in the array controller.
Claim 35
Dependent Claim
28 words
A SIMIMD array processor controller with a CONTROLLER stage according to Claim 7 which executes an essentially SISD command string to provide control for the array of processors.
References Cited (Backward Citations)
No citation records indexed.
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