EP0568385A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for forming contact vias in integrated circuits
Assignee: STMicroelectronics lnc USA
•
Filing: 1993-04-30
•
Granted: —
•
Expires: 2013-04-30
Abstract
Abstract A structure and method for forming contact vias in integrated circuits. An interconnect layer (20) is formed on an underlying layer (22) in an integrated circuit. A buffer region (26) is then formed adjacent to the interconnect layer, followed by forming an insulating layer (28) over the integrated circuit. Preferably, the insulating layer (28) is made of a material which is selectively etchable over the material in the buffer region (26). A contact via (30) is then formed through the insulating layer (28) to expose a portion of the interconnect layer (20). During formation of the contact via, the buffer region (26) acts as an etch stop and protects the underlying layer (22). The buffer region (26) also ensures a reliable contact will be made in the event of an error in contact via placement.
Inventors
- 👤 Michael Edward Haslam
- 👤 Charles Ralph Spinner Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 11:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
109 words
A method for fabricating a contact via in an integrated circuit, comprising the steps of: forming an interconnect layer over portions of an underlying layer in the integrated circuit; forming a buffer region adjacent to the interconnect layer; forming a first insulating layer over the integrated circuit, wherein the first insulating layer is selectively etchable over the buffer region; and forming the contact via through the first insulating layer to expose a portion of the interconnect layer, wherein the buffer region acts as an etch stop and protects the underlying layer during formation of the contact via, and wherein the buffer region allows for an error in via placement.
Claim 2
Dependent Claim
31 words
The method of Claim 1, wherein said step of forming the interconnect layer comprises depositing and patterning a layer of metal over portions of the underlying layer in the integrated circuit.
Claim 3
Dependent Claim
32 words
The method of Claim 1, wherein said step of forming the interconnect layer comprises depositing and patterning a layer of polycrystalline silicon over portions of the underlying layer in the integrated circuit.
Claim 4
Dependent Claim
44 words
The method of Claim 1, wherein said step of forming a buffer region adjacent to the interconnect layer comprises the steps of: depositing a buffer layer over the integrated circuit; and anisotropically etching the buffer layer to form sidewall spacers alongside the interconnect layer.
Claim 5
Dependent Claim
22 words
The method of Claim 4, wherein said buffer layer comprises a material that is not removed during formation of the contact via.
Claim 6
Dependent Claim
13 words
The method of Claim 4, wherein said buffer layer comprises a conductive material.
Claim 7
Dependent Claim
12 words
The method of Claim 4, wherein said buffer layer comprises insulating material.
Claim 8
Dependent Claim
14 words
The method of Claim 7, further comprising the step of siliciding the sidewall spacers.
Claim 9
Dependent Claim
81 words
The method of Claim 1, wherein said step of forming a buffer region adjacent to the interconnect layer comprises the steps of: forming a planarizing layer over the integrated circuit; etching the upper surface of the integrated circuit, wherein a portion of the interconnect layer is exposed; and depositing a first barrier layer over the integrated circuit, wherein the first barrier layer acts as the etch stop and protects the planarizing layer and interconnect layer during formation of the contact via.
Claim 10
Dependent Claim
23 words
The method of Claim 9, wherein said step of forming the planarizing layer comprises depositing a layer of oxide over the integrated circuit.
Claim 11
Dependent Claim
23 words
The method of Claim 9, wherein said step of etching the upper surface of the integrated circuit comprises anisotropically etching the integrated circuit.
Claim 12
Dependent Claim
25 words
The method of Claim 1, wherein said step of forming the contact via comprises anisotropically etching the first insulating layer to form the contact via.
Claim 13
Dependent Claim
30 words
The method of Claim 1, wherein said step of forming a buffer region adjacent to the interconnect layer comprises the step of depositing a barrier layer over the integrated circuit.
Claim 14
Dependent Claim
25 words
The method of Claim 9 or 13 further comprising the step of etching away the portion of the barrier layer exposed in the contact via.
Claim 15
Dependent Claim
95 words
A contact via in an integrated circuit, comprising: an interconnect layer over portions of an underlying layer in the integrated circuit; a buffer region adjacent to the interconnect layer; an insulating layer overlying the integrated circuit, wherein the insulating layer is made of a material which is selectively etchable over the material in the buffer region; a contact via through the insulating layer to expose a portion of the interconnect layer; and a conductive layer overlying portions of the insulating layer and extending into the contact via to make electrical contact with the interconnect layer.
Claim 16
Dependent Claim
19 words
The method of Claim 1 or contact via of Claim 15, wherein said underlying layer comprises a semiconductor substrate.
Claim 17
Dependent Claim
20 words
The method of Claim 1 or contact via of Claim 15, wherein said underlying layer comprises an interlevel dielectric layer.
Claim 18
Dependent Claim
15 words
The contact via of Claim 15, wherein said interconnect layer is made of a metal.
Claim 19
Dependent Claim
15 words
The contact via of Claim 15, wherein said interconnect layer is made of polycrystalline silicon.
Claim 20
Dependent Claim
21 words
The contact via of Claim 15, wherein said buffer region comprises sidewall spacers formed alongside the sidewalls of the interconnect layer.
Claim 21
Dependent Claim
25 words
The contact via of Claim 20, wherein the sidewall spacers are made of a material that is not removed during formation of the contact via.
Claim 22
Dependent Claim
16 words
The contact via of Claim 20, wherein said sidewall spacers are made of a conductive material.
Claim 23
Dependent Claim
14 words
The contact via of Claim 22, wherein said sidewall spacers are made of metal.
Claim 24
Dependent Claim
16 words
The contact via of Claim 20, wherein said sidewall spacers are made of an insulating material.
Claim 25
Dependent Claim
12 words
The contact via of Claim 20, wherein said sidewall spacers are silicided.
Claim 26
Dependent Claim
12 words
The contact via of Claim 20, wherein said insulating layer comprises oxide.
Claim 27
Dependent Claim
22 words
The contact via of Claim 20, wherein said conductive layer covers a portion of the buffer region exposed in the contact via.
Claim 28
Dependent Claim
46 words
The contact via of Claim 15, wherein said buffer region comprises: a planarizing layer overlying the integrated circuit; and a first barrier layer overlying the planarizing layer, wherein the contact via is formed through the first barrier layer to expose a portion of the interconnect layer.
Claim 29
Dependent Claim
14 words
The contact via of Claim 28, wherein said planarizing layer is made of oxide.
Claim 30
Dependent Claim
27 words
The contact via of Claim 28, wherein said first barrier layer acts as an etch stop and protects the planarizing layer during formation of the contact via.
Claim 31
Dependent Claim
25 words
The contact via of Claim 15, wherein said buffer region comprises a barrier layer overlying portions of the integrated circuit adjacent to the contact via.
Claim 32
Dependent Claim
16 words
The contact via of Claim 28 or 31, wherein said barrier layer is made of nitride.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.