EP0568373A2
Expired / Lapsed
EP
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Parallelized magnitude comparator
Assignee: STMicroelectronics lnc USA
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Filing: 1993-04-29
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Granted: —
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Expires: 2013-04-29
Abstract
Abstract A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes of two values more quickly. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. <IMAGE>
Inventors
- 👤 David Charles Mcclure
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 04:48
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
65 words
A magnitude comparator, comprising: a plurality of bit comparators divided into comparator groups that generate an output signal, wherein each of said comparators compares the magnitude between a first bit and a second bit; and a control element, having inputs connected to the outputs of said comparator groups, which selects one of the outputs of said comparator groups to be output from said control element.
Claim 2
Dependent Claim
18 words
The magnitude comparator of claim 1, wherein each said comparator group is independent from every other comparator group.
Claim 3
Dependent Claim
16 words
The comparator group of claim 2, wherein said comparator groups compare a plurality of bits simultaneously.
Claim 4
Dependent Claim
19 words
The comparator group of claim 2, wherein said comparator groups and said control element perform their respective functions simultaneously.
Claim 5
Dependent Claim
23 words
The magnitude comparator of claim 1, wherein each said bit comparator generates a compare output which is input to the subsequent bit comparator.
Claim 6
Dependent Claim
27 words
The magnitude comparator of claim 5, wherein the initial bit comparator of said comparator group has as its compare input a signal set to a predetermined level.
Claim 7
Dependent Claim
25 words
The magnitude comparator of claim 5, wherein each said bit comparator has a first value input, a second value input, and a third value input.
Claim 8
Dependent Claim
31 words
The magnitude comparator of claim 7, wherein said first value input is a one bit value determined by performing logic on the first bit and the second bit to be compared.
Claim 9
Dependent Claim
23 words
The magnitude comparator of claim 8, wherein said second value input is equal to the value of the first bit to be compared.
Claim 10
Dependent Claim
28 words
The magnitude comparator of claim 8, wherein the first bit and the second bit to be compared are a FIFO read count and a FIFO write count, respectively.
Claim 11
Dependent Claim
22 words
The magnitude comparator of claim 7, wherein said third value input is the compare output signal generated by a previous bit comparator.
Claim 12
Dependent Claim
24 words
The magnitude comparator of claim 1, wherein said control element determines which said comparator group contains the highest order bits which do not match.
Claim 13
Dependent Claim
25 words
The control element of claim 12, wherein said control element has a plurality of gates each of which corresponds to one of said comparator groups.
Claim 14
Dependent Claim
26 words
The control element of claim 13, wherein said control element has a plurality of transmission gates each of which corresponds to one of said comparator groups.
Claim 15
Dependent Claim
26 words
The control element of claim 13, wherein said control element has a plurality of tri-stateable gates each of which corresponds to one of said comparator groups.
Claim 16
Dependent Claim
33 words
The comparator of claim 13, wherein said gate receives a first and a second value input which determines whether said gate will allow the first value input to be output from said gate.
Claim 17
Dependent Claim
19 words
The gate of claim 16, wherein the first value input is the output from the corresponding said comparator group.
Claim 18
Dependent Claim
30 words
The gate of claim 17, wherein the second value input is determined by whether the bits compared in the current said comparator group or higher order said comparator groups match.
Claim 19
Dependent Claim
26 words
The gate of claim 16, wherein said gate is capable of not allowing said first value input of said gate to be output from said gate.
Claim 20
Dependent Claim
28 words
The gate of claim 16, wherein only one of the plurality of gates may allow said first value input of said gate to be output from said gate.
Claim 21
Dependent Claim
20 words
The control element of claim 13, wherein there are four said comparator groups each of which has four bit comparators.
Claim 22
Dependent Claim
26 words
The control element of claim 21, wherein each of four said comparator groups corresponds to one said gate for a sixteen bit FIFO flag generation circuit.
Claim 23
Independent Claim
87 words
A method for comparing the magnitude between a first value input and a second value input, comprising the steps of: comparing the magnitude between a first value input and a second value input by grouping bit comparators into comparator groups which generate compare outputs which are input to a control element; and generating a final compare output signal from said control element indicative of whether the magnitude of said first value input is equal to, less than, or greater than the magnitude of said second value input.
Claim 24
Dependent Claim
28 words
The method of claim 23, wherein said comparator groups, which operate in parallel and independently of each other, generate compare outputs which are input to said control element.
Claim 25
Dependent Claim
29 words
The method of claim 23, wherein said control element selects only one of said compare outputs to be output from said control element as a final compare output signal.
Claim 26
Dependent Claim
21 words
The method of claim 23, wherein said comparator groups and said control element operate independently and in parallel with each other.
Claim 27
Dependent Claim
31 words
The method of claim 23, wherein comparison of the magnitude between said first value input and said second value input is useful to generate a flag signal suitable for a FIFO.
References Cited (Backward Citations)
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