Clock synchronization system

Claim 2

The clock of Claim 1, wherein said difference-calculating circuit's first receiving circuit is connected to said clock synchronization circuit for supplying the reference-time signal thereto; said difference-calculating circuit's second receiving circuit comprises a link between said counter and said clock synchronization circuit over which said clock-time signal is applied to said clock synchronization circuit; and wherein said clock synchronization circuit calculates said time difference factor between said reference-time signal and said clock-time signal.

Claim 3

The clock of Claim 2, wherein said clock synchronization circuit is a microprocessor.

Claim 4

The clock of Claim 2, wherein said difference-calculating circuit's first receiving circuit is a reference-time receiver configured to receive the reference-time signal and is connected to said clock synchronization circuit for forwarding the reference-time signal thereto.

Claim 5

The clock of Claim 4, wherein the reference clock is a satellite and wherein said reference-time receiver is adapted to receive the reference-time signal from the satellite.

Claim 6

The clock of Claim 4, wherein:said difference-calculating circuit's second receiving circuit further includes a register connected between said counter and said clock synchronization circuit wherein said register latches said clock-time signal upon receipt of a timing pulse signal, and said clock synchronization circuit calculates said time difference factor from said latched clock-time signal; and wherein said reference-time receiver is connected to said register for supplying said timing pulse signal thereto, and wherein said timing pulse signal is generated when said first reference-time receiver receives the reference-time signal.

Claim 7

The clock of Claim 4, wherein said clock synchronization circuit is a microprocessor.

Claim 8

The clock of Claim 2, wherein said counter advance circuit includes a voltage-controlled oscillator that generates a variable-frequency output signal to produce a variable-frequency clocking signal and wherein said clock synchronization circuit applies a control voltage to said voltage-controlled oscillator to establish said clocking signal.

Claim 9

The clock of Claim 7, wherein said voltage-controlled oscillator output signal is at a frequency higher than the frequency of said clocking signal and wherein said counter advance circuit includes a divider for receiving said voltage-controlled oscillator output signal and producing said clock-time signal therefrom.

Claim 10

The clock of Claim 9, wherein said difference-calculating circuit's first receiving circuit is a reference-time receiver configured to receive the reference-time signal and is connected to said clock synchronization circuit for forwarding the reference-time signal thereto.

Claim 11

The clock of Claim 10, wherein:said difference-calculating circuit's second receiving circuit further includes a register connected between said counter and said clock synchronization circuit wherein said register latches said clock-time signal upon receipt of a timing pulse signal and said clock synchronization circuit calculates said time difference factor from said latched clock-time signal; and wherein said reference-time receiver is connected to said register for supplying said timing pulse signal thereto, and wherein said timing pulse signal is generated when said reference-time receiver receives the reference-time signal.

Claim 12

The clock of Claim 1, wherein: said difference-calculating circuit is part of a maintenance operation point distal from said time counter controller and wherein said maintenance operation point includes: a first receiver for periodically receiving the reference-time signal from the reference clock; a maintenance operation clock connected to said first receiver for maintaining the reference-time signal; a second receiver for receiving said clock-time signal; and, a time-difference-calculating circuit connected to said maintenance operation point clock for receiving the reference-time signal and to said second receiver for receiving said clock-time signal for calculating said time difference factor between the reference-time signal and said clock-time signal and forwarding a difference signal indicative of said time difference factor to said clock synchronization circuit; and whereinsaid clock synchronization circuit includes a receiver for receiving said difference signal from said maintenance operation point.

Claim 13

A clock synchronization system that operates with respect to a reference-time clock that transmits a reference-time signal, comprising: a. a plurality of clocks wherein each said clock includes:a sequentially advanceable counter for maintaining a clock-time signal in response to a clocking signal; a time counter controller having an initialization circuit connected to said counter for establishing a clock initial state as said clock-time signal; a counter advance circuit connected to said counter for generating said clocking signal thereto; and a clock synchronization circuit connected to receive a time difference factor, and connected to said initialization circuit and said counter advance circuit whereby, when said time difference factor is received, said clock synchronization circuit selectively directs said initialization circuit to establish a new clock initial state and said counter advance circuit to change said counter advance signal; b. wherein a first one of said clocks further includes a reference-time receiver for receiving the reference-time signal from the reference clock and connected to said clock synchronization circuit for supplying the reference-time signal thereto; a link between said counter of said first one of said clocks and said clock synchronization circuit for supplying said clock-time signal to said clock synchronization circuit; and wherein said clock synchronization circuit of said first one of said clocks calculates said time difference factor between said reference-time signal and said clock-time signal; c. a maintenance operation point distal from a second one of said clocks including a first receiver for receiving the reference-time signal from the reference clock, a maintenance operation clock connected to said first receiver for maintaining the reference-time signal, a second receiver for receiving said clocktime signal from said second one of said clocks, and a time-difference-calculating circuit connected to said maintenance operation point clock for receiving the reference-time signal and to said second receiver for receiving said clock-time signal for calculating said time difference factor between the reference-time signal and said clock-time signal and forwarding a difference signal indicative of said time difference factor to said second one of said clocks; and d. a receiving unit at said second one of said clocks for receiving said difference signal and connected to said clock synchronization circuit for supplying said time difference factor thereto.

Claim 14

The clock synchronization system of Claim 13, wherein the reference clock is a satellite and wherein said reference-time receivers are adapted to receive the reference-time signal from the satellite.

Claim 15

The clock synchronization system of Claim 13, wherein: said first one of said clocks further includes a register connected between said counter and said clock synchronization circuit wherein said register latches said clock-time signal upon receipt of a timing pulse signal and said clock synchronization circuit calculates said time difference factor from said latched clock-time signal; and said reference-time receiver is connected to said register for supplying said timing pulse signal thereto, and wherein said timing pulse signal is generated when said reference-time receiver of said first one of said clocks receives the reference-time signal.

Claim 16

The clock synchronization system of Claim 13, wherein said counter advance circuits each include a voltage-controlled oscillator that generates a variable-frequency output signal to produce a variable-frequency clocking signal and wherein each said clock synchronization circuit applies a control voltage to said voltage-controlled oscillator associated therewith to establish said clocking signals.

Claim 17

The clock synchronization system of Claim 16, wherein said voltage-controlled oscillator output signals are at higher frequencies than the frequencies of said clocking signals and wherein each said counter advance circuit includes a divider for receiving said voltage-controlled oscillator output signal and producing said clocking signal therefrom.

Claim 18

The clock synchronization system of Claim 13, wherein:said clock synchronization circuits of at least two said clocks are configured so as to cause said counter advance circuits associated therewith to generate clocking signals that are different from each other so as to cause said counters to advance at different rates;said clock initialization circuits of said at least two clocks are configured to adjust said counters associated therewith so that between initializations of said clock times are modified so as to at least periodically be substantially identical to each other.

Claim 19

The clock synchronization system of Claim 18, wherein said clock incrementation circuits of said at least two clocks modify said clock-time signals by periodically incrementally changing said clock-time signal maintained by said counters associated therewith.

Claim 20

A clock synchronization system for synchronizing at least one clock to the time maintained by a reference clock that transmits a reference-time signal, wherein said at least one clock comprises: a. a sequentially advanceable counter for maintaining an elapsed time signal in response to a clocking signal; b. a timer counter controller including: a clock time processor connected to said counter for receiving said elapsed time signal for generating a clock time signal based on said elapsed time and a counter offset value wherein said counter offset value is stored by said clock time processor; a counter advance circuit connected to said counter for generating said clocking signal thereto, wherein said counter advance circuit generates said clocking signal at a variable rate; and a clock synchronization circuit connected to receive a time difference factor, and connected to said clock time processor and said counter advance circuit whereby, when said time difference factor is received, said clock synchronization circuit selectively updates said counter offset value and selectively adjusts said rate at which said counter advance circuit generates said counter advance signal; and c. a difference-calculating circuit including a first receiving circuit for receiving the reference-time signal and a second receiving circuit for receiving said counter clock time signal, and a difference-processing circuit for calculating a difference between the reference-time signal and said clock time signal as said time difference factor and for transmitting said time difference factor to said clock synchronization circuit.

Claim 21

The clock synchronization system of Claim 20, wherein said time counter controller includes a central processing unit and said central processing unit comprises said clock time processor and said clock synchronization circuit.

Claim 22

The clock synchronization system of Claim 21, wherein said difference-calculating circuit's first receiving circuit is connected to said central processing unit for supplying the reference-time signal thereto; and said central processing unit calculates said time difference factor between said reference-time signal and said clock time.

Claim 23

The clock synchronization system of Claim 21, wherein: said difference-calculating circuit is part of a maintenance operation point distal from said time counter controller and wherein said maintenance operation point includes: a first receiver for periodically receiving the reference-time signal from the reference clock; a maintenance operation clock connected to said first receiver for maintaining the reference-time signal; a second receiver for receiving said counter clock time; and, a time-difference-calculating circuit connected to said maintenance operation point clock for receiving the reference-time signal and to said second receiver for receiving said counter clock time for calculating said time difference factor between the reference-time signal and said counter clock time and forwarding a difference signal indicative of said time difference factor to said clock synchronization circuit; and wherein said time counter controller includes a receiver for receiving said difference signal from said maintenance operation point wherein in said receiver is connected to said central processing unit for forwarding said difference signals thereto as said time difference factor.

Claim 24

A clock synchronization system that operates with respect to a reference-time clock that transmits a reference-time signal, comprising: a. a plurality of clocks wherein each said clock includes: a sequentially advanceable counter for maintaining an elapsed-time in response to a clocking signal; a time counter controller including: a clock time processor connected to said counter for receiving the value of said elapsed-time for generating a clock-time signal based on said elapsed time value and on a counter offset value wherein said counter offset value is stored by said clock time processor; a counter advance circuit connected to said counter for generating said clocking signal thereto, wherein said counter advance circuit generates said clocking signal at a viable rate; and a clock synchronization circuit connected to receive a time difference factor, and connected to said clock time processor and said counter advance circuit whereby, when said time difference factor is received, said clock synchronization circuit selectively updates said counter offset value and selectively adjusts said rate at which said counter advance circuit generates said counter advance signal; b. wherein a first one of said clocks further includes a reference-time receiver for receiving the reference-time signal from the reference clock and connected to said clock synchronization circuit for supplying the reference-time signal thereto; a link between said clock time processor of said first one of said clocks and said clock synchronization circuit for supplying said clock-time signal to said clock synchronization circuit; and wherein said clock synchronization circuit of said first one of said clocks calculates said time difference factor between said reference-time signal and said clock-time signal; c. a maintenance operation point distal from a second one of said clocks including a first receiver for receiving the reference-time signal from the reference clock, a maintenance operation clock connected to said first receiver for maintaining the reference-time signal, a second receiver for receiving said clocktime signal from said second one of said clocks, and a time-difference-calculating circuit connected to said maintenance operation point clock for receiving the reference-time signal and to said second receiver for receiving said clock-time signal for calculating said time difference factor between the reference-time signal and said clock-time signal and forwarding a difference signal indicative of said time difference factor to said second one of said clocks; and d. a receiving unit at said second one of said clocks for receiving said difference signal and connected to said clock synchronization circuit for supplying said time difference factor thereto.

Claim 25

The clock synchronization system of Claim 24, wherein: at least two said clocks are provided with clock synchronization circuits are configured so as to cause said counter advance circuits associated therewith to generate clocking signals that are different from each other so as to cause said counters to advance at different rates; andsaid clock synchronization circuits of said at least two clocks are configured to update said counter offset values associated therewith so that between when said time difference factors are received, said clock time processors will generate clock times that are substantially identical to each other.

Claim 26

The clock synchronization system of Claim 25, wherein said clock synchronization circuits of said at least two clocks update said counter offset values by periodically incrementally said counter offset values.

Claim 27

A clock network for providing time signals and reference signals comprising: a plurality of clocks, each said clock including: a sequentially advanceable counter for maintaining a time value in response to a reference signal; a signal generator for producing said reference signal for application to said counter associated therewith wherein, at least two signal generators are configured to produce different said reference signals so that said counters associated therewith will advance at different rates; a time value processing circuit connected to said counter for producing a time signal based on said time value wherein, said clock time value processing circuits associated with said at least two signal generators are configured to produce clock times based on said dissimilar time values that are substantially identical to each other.

Claim 28

The clock network of Claim 27, wherein said counters maintain clock times upon which said time signals are produced and said time value processing circuits periodically increment said counters so that said clock times are periodically substantially identical to each other.

Claim 29

The clock network of Claim 28, wherein said reference signals are viable frequency signals and said signal generators produce said reference signals at different frequencies.

Claim 30

The clock network of Claim 27, wherein: said counters maintain elapsed time counts; said time value processing circuits maintain separate counter offset values for combining with said elapsed time counts to produce time signals; and said time value processing circuits periodically incrementally change said counter offset values so that said time signals are periodically substantially identical with each other.

Claim 31

The clock network of Claim 30, wherein said reference signals are variable frequency signals and said signal generators produce said reference signals at different frequencies.

Claim 32

A broadcast network comprising: a plurality of radio transmitters for broadcasting radio signals at a carrier frequency, each said transmitter including a carrier frequency control circuit for establishing said carrier frequency of said transmitter, wherein said carrier frequency control circuit establishes said carrier frequency based on a reference signal; a plurality of clock circuits, wherein each said clock circuit is associated with a corresponding one of said plurality of radio transmitters, each said clock circuit including: a sequentially advanceable counter for maintaining a time value in response to said reference signal; a signal generator for producing said reference signal for application to said carrier frequency control unit and said counter associated therewith wherein, at least two clock signal generators are configured to produce different said reference signals so that said transmitters associated therewith will broadcast at different carrier frequencies and said counters associated therewith will advance at different rates so as to cause said counters to maintain dissimilar time values; a time value processing circuit connected to said counter for producing a clock time based on said time value wherein, said clock time value processing circuits associated with said at least two signal generators are configured to produce clock times based on said dissimilar time values that are substantially identical to each other.

Claim 33

The broadcast network of Claim 32, wherein said counters maintain clock times upon which said time signals are produced and said time value processing circuits periodically increment said counters so that said clock times are periodically substantially identical to each other.

Claim 34

The broadcast network of Claim 33, wherein said reference signals are variable frequency signals and said signal generators produce said reference signals at different frequencies.

Claim 35

The broadcast network of Claim 32, wherein: said counters maintain elapsed time count; said time value processing circuits maintain separate counter offset values for combining with said elapsed time counts to produce time signals; and said time value processing circuits periodically incrementally change said counter offset values so that said time signals are periodically substantially identical with each other.

Claim 36

The broadcast network of Claim 35, wherein said reference signals are variable frequency signals and said signal generators produce said reference signals at different frequencies.