EP0562737A2
Expired / Lapsed
EP
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Flash memory and data processor
Assignee: Hitachi Ltd
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Filing: 1993-03-10
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Granted: —
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Expires: 2013-03-10
Abstract
Abstract Of a pair of memory cells Q21 and Q31 sharing the source S1 of the flash memory cell, only one of the paired memory cells is erased, and the other memory cell is then erased. Specifically, the memory cells on an even row A2 is erased, and the memory cells on an odd row A3 are then erased. An erasure preventing voltage is applied to the odd rows, while the even rows are being erased, and to the even rows while the odd rows are being erased.
Inventors
- 👤 Kazuyosi Siba
- 👤 Masaaki Terasawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 21:20
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
218 words
A nonvolatile memory device comprising: a memory array arranged in matrix with a plurality of pairs of memory cells, of which the first memory cell and the second memory cell have their sources coupled to each other, wherein each of said first and second memory cells has a drain, and a floating gate and a control gate over a channel region formed between said source and said drain; a plurality of source lines contained in said memory array, wherein each of said plurality of source lines is coupled to said source of each of said paired memory cells; a plurality of first word lines and a plurality of second word lines contained in said memory array, wherein one of said plurality of first word lines is coupled to said control gate of each of said first memory cells arranged in a row direction whereas one of said plurality of second word lines is coupled to said control gate of each of said second memory cells arranged in the row direction; first voltage supply means for supplying a first erasing voltage to at least one of said source lines; and second voltage supply means for feeding a second erasing voltage to said plurality of first word lines and an erasure preventing voltage to said plurality of second word lines.
Claim 2
Dependent Claim
27 words
The nonvolatile memory device according to Claim 1, further comprising control means for outputting one of first and second control signals to said second voltage supply means.
Claim 3
Dependent Claim
87 words
The nonvolatile memory device according to Claim 2, wherein when said control means outputs said first control signal said second voltage supply means feeds said second erasing voltage to said plurality of first word lines and said erasure preventing voltage to said second plurality of second word lines, and wherein said control means outputs said second control signal said second voltage supply means feeds said second erasing voltage to said plurality of second word lines and said erasure preventing voltage to said plurality of first word lines.
Claim 4
Dependent Claim
45 words
The nonvolatile memory device according to Claim 3, wherein said first voltage supply means includes a plurality of voltage supply circuits, wherein one of said voltage supply circuits selected in accordance with a select signal coming from said control means feeds said first erasing voltage.
Claim 5
Dependent Claim
256 words
A microcomputer comprising: a CPU; memory means having its content rewritten by said CPU; and a nonvolatile memory device including: a memory array arranged in matrix with a plurality of pairs of memory cells, of which the first memory cell and the second memory cell have their sources coupled to each other, wherein each of said first and second memory cells has a drain, and a floating gate and a control gate over a channel region formed between said source and said drain; a plurality of source lines contained in said memory array, wherein each of said plurality of source lines is coupled to said source of each of said paired memory cells; a plurality of first word lines and a plurality of second word lines contained in said memory array, wherein one of said plurality of first word lines is coupled to said control gate of each of said first memory cells arranged in a row direction whereas one of said plurality of second word lines is coupled to said control gate of each of said second memory cells arranged in the row direction; first voltage supply means selected according to the content of said memory means for supplying a first erasing voltage to at least one of said source lines; select means for selecting one of said pluralities of first and second word lines on the basis of an address fed thereto; and second voltage supply means for feeding a second erasing voltage to one of the word lines selected by said select means.
Claim 6
Dependent Claim
22 words
The microcomputer according to Claim 5, wherein said second voltage supply means feeds an erasure preventing voltage to the word lines unselected.
Claim 7
Dependent Claim
36 words
The microcomputer according to Claim 6, further comprising control means for outputting one of first and second control signals to said second voltage supply means on the basis of a control signal coming from said CPU.
Claim 8
Dependent Claim
85 words
The microcomputer according to Claim 7, wherein when said control means outputs said first control signal said second voltage supply means feeds said second erasing voltage to said plurality of first word lines and said erasure preventing voltage to said second plurality of second word lines, and wherein said control means outputs said second control signal said second voltage supply means feeds said second erasing voltage to said plurality of second word lines and said erasure preventing voltage to said plurality of first word lines.
Claim 9
Dependent Claim
66 words
The microcomputer according to Claim 8, wherein said memory means is a register having: an erase designating bit for designating an erasing operation; a write designating bit for designating a writing operation; a verify designating bit for designating a verifying operation; and an erase block designating bit for designating at least one of said source lines to be coupled to the memory cells to be erased.
Claim 10
Dependent Claim
43 words
The microcomputer according to Claim 9, wherein said first voltage supply means includes a plurality of voltage supply circuits, wherein one of said voltage supply circuits selected in accordance with the erasure block designating bit of said register feeds said first erasing voltage.
References Cited (Backward Citations)
No citation records indexed.
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