EP0561271A2
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EP
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Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
Assignee: Hitachi Ltd
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Filing: 1993-03-11
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Granted: —
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Expires: 2013-03-11
Abstract
Abstract An electrically rewritable flash memory device has a memory cell array including a plurality of memory cells (MC) arranged in rows and columns and is divided into a plurality of memory blocks (MB) having different memory capacities. Each memory block includes one or more rows of memory cells having their control gates connected to their associated word line conductors (WL) extending in a row direction. Sources of all of the memory cells in each memory are connected to one single common conductor (SL) associated therewith and extending in the row direction. Drains of memory cells are connected to respective data line conductors (DL) extending in a column direction. A common voltage control circuit (ERS) is provided for each of the memory blocks for applying a first potential (0V) to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential (Vddi--3.5V) higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a central processing unit (CPU) and the above-mentioned electrically rewritable flash memory (FMRY) formed in a single semiconductor chip (CHP) includes an input terminal (Pmode) for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the central processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit (PRW) externally connectable to the microcomputer.
Inventors
- 👤 Kiyoshi Arukasaru Musashino 210 Matsubara
- 👤 Naoki Yashiki
- 👤 Shiro Baba
- 👤 Takashi Neokopo Kokubunji 211 Ito
- 👤 Hirofumi Mukai
- 👤 Masanao Sato
- 👤 Masaaki Terasawa
- 👤 Kenichi Kuroda
- 👤 Kazuyoshi Shiba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 21:08
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7821; G06F15/7814; G06F9/00; G06F9/06; G06F9/44; G06F9/445; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10; G11C16/102; G11C16/105; G11C16/12; G11C16/26; G11C16/30; G11C16/34; G11C16/3418; G11C16/3427; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10B69/00; G11C16/14; G11C16/16; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
131 words
A microcomputer comprising a central processing unit (CPU) and an electrically rewritable flash memory (FMRY) capable of storing data to be processed by said central processing unit, said central processing unit and said flash memory being formed in a single semiconductor chip (CHP), wherein: said flash memory includes a plurality of memory blocks (SMB, LMB) having different memory capacities, each of said memory blocks having memory cells arranged so as to be simultaneously erasable; an input terminal (Pmode) for receiving an operation mode signal for switching the microcomputer between a first operation mode in which said flash memory is rewritten under control of said central processing unit and a second operation mode in which said flash memory is rewritten under control of separate writing means (PRW) externally connectable to the microcomputer.
Claim 2
Dependent Claim
48 words
A microcomputer according to Claim 1 further comprising a random access memory (RAM) formed in said single semiconductor chip (CHP), wherein at least one of said memory blocks is a relatively small memory block (SMB) having a memory capacity not larger than that of said random access memory.
Claim 3
Dependent Claim
62 words
A microcomputer according to Claim 2 further comprising a read only memory (ROM) formed in said single semiconductor chip (CHP), wherein a rewriting control program to be executed by said central processing unit (CPU) for rewriting said flash memory (FRMY) when the microcomputer is switched to said first operation mode is stored one of said flash memory and said read only memory.
Claim 4
Dependent Claim
99 words
A microcomputer according to Claim 3, wherein said rewriting control program contains modification of addresses of a predetermined area of said random access memory (RAM) such that the modified addresses overlap those of said relatively small memory block (SMB), writing of information in said predetermined area of the random access memory, restoration of said modified addresses of said predetermined area of said random access memory to its former addresses after the information writing, and rewriting of said relatively small memory block with said information written in said predetermined area of said random access memory whose addresses have been restored.
Claim 5
Dependent Claim
56 words
A microcomputer according to Claim 3, wherein said rewriting control program contains transference of information stored in said relatively small memory block (SMB) to said random access memory (RAM), updating of at least a part of said transferred information on said random access memory, and rewriting of said relatively small memory block with the updated information.
Claim 6
Dependent Claim
108 words
A microcomputer comprising a central processing unit (CPU), an electrically rewritable flash memory (FMRY) capable of storing data to be processed by said central processing unit and a random access memory (RAM), said central processing unit, said flash memory and said random access memory being formed in a single semiconductor chip (CHP), wherein: said flash memory includes a plurality of memory blocks (SMB, LMB) having memory capacities different from each other, each of said memory blocks having memory cells arranged so as to be simultaneously erasable; and at least one of said memory blocks (SMB) has a memory capacity not larger than that of said random access memory.
Claim 7
Dependent Claim
123 words
A microcomputer according to Claim 6 further comprising means for storing a rewriting control program to be prosecuted by said central processing unit (CPU) for rewriting said flash memory (FMRY), wherein said rewriting control program contains modification of addresses of a predetermined area of said random access memory (RAM) such that the modified addresses overlap those of said relatively small memory block (SMB), writing of information in said predetermined area of the random access memory, restoration of said modified addresses of said predetermined area of said random access memory to its former addresses after the information writing, and rewriting of said relatively small memory block with said information written in said predetermined area of said random access memory whose addresses have been restored.
Claim 8
Dependent Claim
32 words
A microcomputer according to Claim 7, wherein said rewriting control program storing means is one of said flash memory and a read only memory (ROM) formed in said single semiconductor chip (CHP).
Claim 9
Dependent Claim
80 words
A microcomputer according to Claim 6 further comprising means for storing a rewriting control program to be prosecuted by said central processing unit (CPU) for rewriting said flash memory (FMRY), wherein said rewriting control program contains transference of information stored in said relatively small memory block (SMB) to said random access memory (RAM), updating of at least a part of said transferred information on said random access memory, and rewriting of said relatively small memory block with the updated information.
Claim 10
Dependent Claim
32 words
A microcomputer according to Claim 9, wherein said rewriting control program storing means is one of said flash memory and a read only memory (ROM) formed in said single semiconductor chip (CHP).
Claim 11
Dependent Claim
32 words
A microcomputer according to Claim 1, wherein said flash memory (FRMRY) further includes a register (CREG) for rewritably holding information designating a memory block to be subjected to a simultaneous erasure operation.
Claim 12
Dependent Claim
108 words
A microcomputer comprising: a central processing unit (CPU); an electrically rewritable flash memory (FMRY); flash memory rewriting I/O port means (PORTdata, PORTaddr, PORTcont) capable of being coupled to a ROM writer (PRW) for rewriting said flash memory; switch means (SWITCH) located between said central processing unit and said flash memory; and a rewriting mode decision means (CONT) responsive to an externally supplied operation mode signal for controlling said switch means and said flash memory rewriting I/O port means, said central processing unit, said flash memory, said flash memory I/O port means, said switching means and said rewriting mode decision means being formed in a single semiconductor chip (CHP).
Claim 13
Dependent Claim
158 words
A microcomputer according to Claim 12, wherein: when said operation mode signal is a first operation mode signal (MD1), said rewriting mode decision means (CONT) renders said switching means (SWITCH) conductive and said flash memory rewriting I/O port means inoperative so that said central processing unit (CPU) and said flash memory (FMRY) are coupled to each other for rewriting said flash memory by said central processing unit and no signal is received/transmitted through said flash memory rewriting I/O port means (PORTdata, PORTaddr, PORTcont); and when said operation mode signal is a second operation mode signal (MD2), said rewriting mode decision means renders said switching means non-conductive and said flash memory rewriting I/O port means operative so that said central processing unit and said flash memory are isolated from each other and signals are allowed to be received/transmitted between said flash memory-rewriting I/O port means and said ROM writer (PRW) for rewriting said flash memory by said ROM writer.
Claim 14
Dependent Claim
50 words
A microcomputer according to Claim 13, further comprising means (ROM) for storing therein a rewriting control program to be executed by said central processing unit (CPU) for controlling rewriting of said flash memory (FMRY) by said central processing unit, said storing means being formed in said single semiconductor chip (CHP).
Claim 15
Dependent Claim
39 words
A microcomputer according to Claim 13, wherein said flash memory has a rewriting control program stored therein to be executed by said central processing unit (CPU) for controlling rewriting of said flash memory (FMRY) by said central processing unit.
Claim 16
Dependent Claim
279 words
An electrically rewritable flash memory device comprising: a memory cell array including a plurality of memory cells (MC) arranged in rows and columns, each of said memory cells (MC) including a non-volatile memory element having a source (13) and a source (13), and a control gate (11); a plurality of word line conductors (WL) extending in parallel with one another in a row direction, control gates of memory cells in one row being connected in common to one word line conductor; a plurality of data line conductors (DL) extending in parallel with one another in a column direction, drains of memory cells in one column being connected in common to one data line conductor; a plurality of source line conductors (SL) extending in said row direction, sources of at least one row of memory cells being connected in common to one source line conductor such that said at least two rows of memory cells having their sources connected in common to one source line conductor form a memory block, memory blocks (MB) so formed having different memory capacities; and a plurality of source voltage control means (ERS), one provided for each of said memory blocks, said source voltage control means applying a first potential (0V) to a source line conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential (Vddi--3.5V) higher than said first potential to a source line conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation.
Claim 17
Dependent Claim
46 words
An electrically rewritable flash memory device according to Claim 16, in which said source voltage control means (ERS) is capable of applying a third potential (Vpp) to a source line conductor for a memory block having memory cells to be simultaneously erased in an erasing operation.
Claim 18
Dependent Claim
49 words
An electrically rewritable flash memory device according to Claim 16, in which said memory blocks include at least one large memory block (LMB) containing a relatively large number of word line conductors and at least one small memory block (SMB) containing a relatively small number of word line conductors.
Claim 19
Dependent Claim
128 words
An electrically rewritable flash memory device according to Claim 18, in which said at least one large memory block is arranged to form a first memory block group and said at least one small memory block is arranged to form a second memory block group, the flash memory device further comprising a transfer gate circuit (TGC) arranged between said first and second memory block groups, a selection circuit (YSEL) for selecting a data line conductor in a writing/reading operation, said selection circuit being arranged such that said first memory block group is sandwiched between said transfer gate circuit and said selection circuit, said selection circuit, and a control circuit (250) for rendering said transfer gate circuit when said first memory block group is subjected to a writing operation.
Claim 20
Dependent Claim
42 words
A microcomputer comprising an electrically rewritable flash memory device according to Claim 16 and a central processing unit (CPU) capable of accessing said flash memory, said flash memory device and said central processing unit being formed in a single semiconductor chip (CHP).
Claim 21
Dependent Claim
52 words
A microcomputer according to Claim 20, wherein said flash memory device further comprises an externally rewritable register (CREG, 231) holding at least one of information as to which memory block should be subjected to a simultaneous erasing operation and information as to which memory block should be subjected to a rewriting operation.
Claim 22
Dependent Claim
411 words
An electrically rewritable flash memory device comprising: a memory cell array including a plurality of memory cells (MC) arranged in rows and columns, each of said memory cells (MC) including a non-volatile memory element having first and second semiconductor regions (13) formed in a first surface portion of a semiconductor substrate (1), a floating gate (7) formed over and insulated from a second surface portion of said semiconductor substrate between said said first and second semiconductor regions, and a control gate (11) formed over and insulated from said floating gate; a plurality of first conductors (WL) extending in parallel with one another in a row direction over said semiconductor substrate, control gates of memory cells in one row being connected in common to one first conductor; a plurality of second conductors (DL) extending in parallel with one another in a column direction over said semiconductor substrate, first semiconductor regions of memory cells in one column being connected in common to one second conductor; a plurality of common conductors (SL) extending in said row direction over said semiconductor substrate, second semiconductor regions of at least two rows of memory cells being connected in common to one common conductor such that said at least one row of memory cells having their second semiconductor regions connected in common to one common conductor form a memory block, memory blocks (MB) so formed having different memory capacities; a plurality of common voltage control circuits (ERS) formed in said substrate, one provided for each of said memory blocks, for generating a common voltage (Vs) assuming at least first and second voltage values (Vpp, Vddi); and a control circuit (230, 231, 240) formed in said substrate for generating a control signal (2414) indicating which of said memory blocks is subjected to an erasing/writing operation, said control signal being supplied to said plurality of common voltage control circuits (ERS) so that individual common voltage control circuits apply to their associated common conductors common voltages each having one of said first and second voltage values depending on said control signal to effect a writing operation with a common voltage of said second voltage value (Vddi) applied to a common conductor for a memory block (31) which does not contain a memory cell selected for the writing operation and to effect a simultaneous erasing operation with a common voltage of said first voltage value (Vpp) applied to a common conductor for a memory block (20) selected for a simultaneous erasing operation.
Claim 23
Dependent Claim
33 words
An electrically rewritable flash memory device according to Claim 22, wherein said second voltage (Vddi) is not higher than a voltage (Vp) on that second conductor which is selected in a writing operation.
Claim 24
Dependent Claim
164 words
An electrically rewritable flash memory device according to Claim 22, further comprising a gate circuit (TGC) and a second conductor selection circuit (YSEL) for selecting one of said second conductors, both formed in said substrate, wherein the memory capacities of said plurality of memory blocks are monotonously changed as viewed in a lengthwise direction of said second conductors, said gate circuit and said second conductor selection circuit are arranged such that at least one of said memory blocks is sandwiched between them, said at least one sandwiched memory block being other than a memory block having the smallest memory capacity among said memory blocks and forming a first memory block group while the other memory blocks form a second memory block group, and wherein the second conductors in said first memory block groups and those of in said second memory block groups are interconnected by said gate circuit so that said second memory block group is made inoperative when said gate circuit is non-conductive.
Claim 25
Dependent Claim
80 words
An electrically rewritable flash memory device according to Claim 24, further comprising first and second rows of dummy cells (DC4-DC6, DC1-DC3) formed between said first memory block group and said gate circuit (TGC) and between said gate circuit and said second memory block group, respectively, in said substrate to thereby suppress abrupt changes of generally periodic patterns of said memory cells (MC) and first conductors (WL) caused by said gate circuit provided between said first and second memory block groups.
Claim 26
Dependent Claim
101 words
An electrically rewritable flash memory device according to Claim 22, further comprising a plurality of gate circuits (TGC) and a second conductor selection circuit (YSEL) for selecting one of said second conductors, both formed in said substrate, wherein said gate circuits (TGC) are provided one for each of said memory blocks (MB) and arranged such that first semiconductor regions (13) of memory cells in each column in each memory block are connected in common to one second conductor (DL) through its associated gate circuit so that each of said memory blocks is made inoperative when its associated gate circuit is non-conductive.
References Cited (Backward Citations)
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