EP0561131A2
Expired / Lapsed
EP
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Module level electronic redundancy
Assignee: International Business Machines Corp
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Filing: 1993-01-29
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Granted: —
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Expires: 2013-01-29
Abstract
Abstract A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.
Inventors
- 👤 Robert Dean Adams
- 👤 Henry August Bonges Iii
- 👤 James William Dawson
- 👤 Erik Leigh Hedberg
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/72; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/78
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
122 words
An array built in self test (ABIST) system formed on a semiconductor chip comprising a memory array including a plurality of word lines, one of which is faulty, and a redundant word line, means for identifying said faulty word line, means for storing an address of said faulty word line, a plurality of fuses, interface circuit means coupling said address storing to said plurality of fuses, enabling signal means coupled to said interface circuit means for blowing selected one or more of said plurality of fuses depending upon the address of said faulty word line stored in said storing means, and switching means coupled to outputs of said interface circuit means for replacing said faulty word line with said redundant word line.
Claim 2
Dependent Claim
32 words
An array built in self test (ABIST) system as set forth in claim 1 wherein said enabling signal means includes a terminal on said semiconductor chip having an enabling signal applied thereto.
Claim 3
Dependent Claim
25 words
An array built in self test (ABIST) system as set forth in claim 2 wherein said terminal is a pad disposed on said semiconductor chip.
Claim 4
Dependent Claim
30 words
An array built in self test (ABIST) system as set forth in claim 3 wherein said enabling signal means further includes a master fail signal derived from said identifying means.
Claim 5
Dependent Claim
29 words
An array built in self test (ABIST) system as set forth in claim 1 wherein each of the fuses of said plurality of fuses is made of doped polysilicon.
Claim 6
Dependent Claim
53 words
An array built in self test (ABIST) system as set forth in claim 4 further including a voltage supply source connected to a first end of each of the fuses of said plurality of fuses, and a second end of said plurality of fuses being connected to outputs of said interface circuit means.
Claim 7
Dependent Claim
31 words
An array built in self test (ABIST) system as set forth in claim 6 wherein a second end of one of said plurality of fuses is coupled to said identifying means.
Claim 8
Dependent Claim
22 words
An array built in self test (ABIST) system as set forth in claim 1 wherein said switching means includes an address decoder.
Claim 9
Dependent Claim
155 words
An array built in self test (ABIST) system formed on a semiconductor chip and having a power supply source of a given voltage comprising a memory array including a plurality of word lines, one of which is faulty, and a redundant word line, means for identifying said faulty word line, means for storing a multi-bit address of said faulty word line, a plurality of fuses, each being selectively coupled to said power supply source, interface circuit means coupling respective ones of the bits of said multi-bit address to respective ones of said plurality of fuses, enabling signal means coupled to said interface circuit means for connecting selected ones of said plurality of fuses to said power supply source depending upon the address of said faulty word line stored in said address storing means, and switching means coupled to outputs of said interface circuit means for replacing said faulty word line with said redundant word line.
Claim 10
Dependent Claim
32 words
An array built in self test (ABIST) system as set forth in claim 9 wherein said enabling signal means includes a terminal on said semiconductor chip having an enabling signal applied thereto.
Claim 11
Dependent Claim
25 words
An array built in self test (ABIST) system as set forth in claim 10 wherein said terminal is a pin disposed on said semiconductor chip.
Claim 12
Dependent Claim
30 words
An array built in self test (ABIST) system as set forth in claim 11 wherein said enabling signal means further includes a master fail signal derived from said identifying means.
Claim 13
Dependent Claim
22 words
An array built in self test (ABIST) system as set forth in claim 12 wherein said switching means includes an address decoder.
Claim 14
Dependent Claim
143 words
An array built in self test (ABIST) system formed on a semiconductor chip having a pad disposed thereon comprising a memory array including a plurality of word lines, one of which is a faulty word line, and a redundant word line, data compression means for providing a signal to identify said faulty word line, failed address register means responsive to said signal for storing an address of said faulty word line, electrical fuse blow interface means responsive to said signal applied to said pad, redundancy fuse circuit means including a plurality of fuses coupled to outputs of said electrical fuse blow interface means for blowing selected fuses of said plurality of fuses depending upon the address of said faulty word line, and address decoder means coupled to said redundancy fuse circuit means for substituting said redundant word line for said faulty word line.
Claim 15
Dependent Claim
24 words
An array built in self test (ABIST) system as set forth in claim 14 wherein each of said fuses is made of doped polysilicon.
Claim 16
Independent Claim
140 words
A system formed on a semiconductor chip comprising an electrical terminal disposed on said chip having a fuse blow enabling signal applied thereto, a memory array including a plurality of word lines having a faulty word line and a redundant word line, means for providing a control signal to identify said faulty word line, means responsive to said control signal for storing an address of said faulty word line, a plurality of fuses, interface circuit means responsive to said control signal and to said fuse blow enable signal coupling said address storing means to said plurality of fuses for blowing selected one or more of said plurality of fuses depending upon the address of said faulty word line, and switching means coupled to outputs of said interface circuit means for replacing said faulty word line with said redundant word line.
Claim 17
Dependent Claim
15 words
A system as set forth in claim 16 wherein said terminal is a conductive pad.
Claim 18
Dependent Claim
24 words
A system as set forth in claim 16 wherein said means for storing includes a register and said switching means includes an address decoder.
Claim 19
Dependent Claim
153 words
In a memory device mounted on a substrate including a plurality of lines of first memory cells, each line having a discrete x-bit address, a fault detection and recovery apparatus comprising at least one line of second spare memory cells, first means for temporarily storing an x-bit address of at least one of said plurality of lines of first memory cells determined to be faulty, fuse means for permanently storing said x-bit address of said at least one of said plurality of lines of first memory cells so that said at least one line of second spare memory cells is substituted for said at least one of said plurality of first memory cells, and third means responding to an enable signal for programming said fuse means to permanently store said x-bit address from said first means, said third means preventing said fuse means from being programmed in the absence of said enable signal.
Claim 20
Dependent Claim
56 words
In a memory device mounted on a substrate as set forth in claim 19 wherein said fuse means includes a plurality of fuses each having a first end connected to a voltage supply source and said third means is coupled to a second end to a second end of the fuses of said plurality of fuses.
Claim 21
Dependent Claim
116 words
An array built in self test (ABIST) system formed on a semiconductor chip packaged within a module comprising an array having a faulty element therein and a redundant element, means for storing an address signal of said faulty element, an electrical fuse having a first end thereof connected to a first terminal of a voltage supply source, a terminal disposed on said semiconductor chip having an enabling signal applied thereto, and means responsive to said enabling signal and to the address signal for selectively coupling a second end of said electrical fuse to a second terminal of said voltage supply source to switch signals representative of the address of said faulty element to said redundant element.
Claim 22
Dependent Claim
139 words
An array built in self test (ABIST) system as set forth in claim 10 wherein said identifying means includes an output having a master fail signal thereon and wherein said interface circuit means includes at least one NAND circuit having first and second inputs and an output and an OR circuit having first and second inputs and an output, the first input of said NAND circuit being connected to said storing means, the second input of said NAND circuit being coupled to the output of said identifying means, the first input of said OR circuit being connected to the terminal of said enabling signal means, the second input of said OR circuit being connected to the output of said NAND circuit and the output of said OR circuit being coupled to the second end of said plurality of fuses.
Claim 23
Dependent Claim
103 words
An array built in self address (ABIST) system as set forth in claim 22 wherein said interface circuit means further includes an inverter having an input and an output disposed between the output of said OR circuit and the second end of said plurality of fuses and an N-channel field effect transistor having a control electrode connected between the terminal of said enabling signal means and the second end of said plurality of fuses, the input of said inverter being connected to the output of said OR circuit and the output of said inverter being connected to the control electrode of said transistor.
References Cited (Backward Citations)
No citation records indexed.
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