Memory column redundancy and localized column redundancy control signals

Claim 2

A memory (20), comprising: a left array (21) having a top and a bottom; a left array of redundant columns (23) below said left array; a right array (22) having a top and a bottom; a right array of redundant columns (24) below said right array; a left write global data line (37) disposed left of and coupled to said left array (21); a right write global data (43) disposed right of and coupled to said right array (22); a left redundant write global data line (39) disposed left of and coupled to said left array of redundant columns (23); a right redundant write global data line (28) disposed right of coupled to said right array of redundant columns (24); a left write portion (30A) for selectively coupling a first data input signal to either said left write global data line (37) or to said left redundant write global data line (39) in response to a first fuse (32) operation; and a right write portion (30D) for selectively coupling a second data input signal to either said right global data line (43) or to said right redundant global data line (28) in response to a second fuse (88) operation.

Claim 3

The memory (20) of Claim 2, further comprising: a read global data line (29) coupled to said left array (21) and to said right array (22) and disposed therebetween, for reading data from said left and right arrays (21 and 22); a redundant read global data line (44) coupled to said left and right arrays of redundant columns (23 and 24) and disposed therebetween, for reading data from said left array of redundant columns (23) and said right array of redundant columns (24); a top read portion (50B) coupled to said read global data line (29) and to said redundant read global data line (44) and disposed above said left and right arrays (21 and 22), for providing a first data signal conducted by either, said read global data line (29) or said redundant read global data line (44), in response to a third fuse (85) operation; and a bottom read portion (50A) coupled to said read global data line (29) and to said redundant read global data line (44) and disposed below said left and said right redundant arrays (23 and 24), for selectively coupling a second data signal from either, said read global data line (29) or said redundant read global data line (44), in response to a fourth fuse (59) operation.

Claim 4

A memory with column redundancy and localized column redundancy control signals (20), comprising: an array of memory elements (21) organized in rows and columns; a redundant array of redundant columns (23); pluralities of read and write global data lines (29 and 37) coupled to said array (21); pluralities of redundant read and write global data lines (44 and 39) coupled to said redundant array (23); an address comparator (200) including address fuse means (300) for providing a plurality of defective address signals in response to an input address and a corresponding plurality of fuse signals; a write portion (30A) coupled to write fuse means (32) for providing an input/output data signal to a selected one of said redundant write global data lines (39) in response to said defective address signals during a write cycle; and a read portion (50A) coupled to read fuse means (59) for receiving said input/output data signal and for providing said input/output data signal to a selected one of said redundant read global data lines (44) in response to said defective address signals during a read cycle.

Claim 5

A memory (20) having a read mode and a write mode, comprising: a plurality of arrays (21 and 22), each comprising a plurality of intersecting rows and columns of memory cells; a plurality of sets of write global data line pairs (37 and 41), each set coupled to a corresponding array (21 and 22) for carrying data to selected columns of said corresponding array; a plurality of sets of read global data line pairs (29), each set coupled to an array (21 and 22), for carrying data from selected columns of said array; a plurality of redundant columns of memory cells (23 and 24); a plurality of sets of redundant write global data line pairs (28 and 39), each coupled to a corresponding redundant column, for carrying data to said redundant columns (23 and 24); a plurality of sets of redundant read global data line pairs (44), each coupled to said redundant columns (23 and 24) for carrying data from said redundant columns (23 and 24); comparator means (45) for detecting when a defective column in one of said arrays (21 and 22) is to be replaced by a redundant column; a plurality of write fuse means (32) for selecting one of said redundant columns to replace a defective column when the memory (20) is in the write mode; a plurality of write portions (30A and 30B), each coupled to a corresponding one of said sets of write global data line pairs (37 and 41), a corresponding one of said sets of redundant write global data line pairs (26 and 39), a corresponding one of said write fuse means (32 and 25), and to said comparator means (45) for either writing data onto said write global data line pairs (37 and 41), or for writing data onto said redundant write global data line pairs (26 and 39) selectively in response to said comparator means (45) detecting a defective column when the memory (20) is in the write mode; a plurality of read fuse means (59 and 85) for selecting which redundant column is to replace a defective column when the memory (20) is in the read mode; and a plurality of read portions (50A and 50B), each coupled to a corresponding one of said sets of read global data line pairs (29), a corresponding one of said sets of redundant read global data line pairs (44), a corresponding one of said read fuse means (59 and 85), and to said comparator means (45) for either reading data from said read global data line pairs (29), or for reading data from said redundant read global data line pairs (44) selectively in response to said comparator means (45) detecting a defective column when the memory (20) is in the read mode.

Claim 6

A memory (20) having a read mode and a write mode, comprising: a left and a right array of memory cells (21 and 22) each comprising a plurality of blocks of intersecting rows and columns of memory cells; said left array (21) having a top portion and a bottom portion and said right array (22) having a top portion and a bottom portion; four sets of write global data line pairs (37, 42, 43, and 41), each set of write global data line pairs (37, 42, 43, and 41) coupled to corresponding ones of top and bottom portions of said left and right arrays (21 and 22) for carrying data to selected columns of said portions of said array; four sets of read global data line pairs (29), each set of read global data line pairs (29) coupled to corresponding ones of top and bottom portions of said left and right arrays (21 and 22) for carrying data from selected columns of said portion of said array; a left plurality of sets of redundant columns (23) of memory cells located at the bottom of said left array (21), for replacing defective columns in said left array (21); a right plurality of sets of redundant columns (24) of memory cells located at the bottom of said right array (22), for replacing defective columns in said right array (22); a plurality of sets of redundant write global data line pairs (26, 39, 27, and 28), each coupled to a corresponding redundant column for carrying data to said redundant column; a plurality of redundant read global data line pairs (44), each coupled to a corresponding redundant column for carrying data from said redundant column; comparator means (45) for detecting when a defective column in said left or right array (21 and 22) is to be replaced by a redundant column; a plurality of write fuses (25, 32, 87, and 88) for selecting one of said redundant columns to replace a defective column when the memory (20) is in the write mode; a plurality of write portions (30A, 30B, 30C, and 30D), each coupled to a corresponding one of said sets of write global data line pairs (37, 42, 43, and 41), a corresponding one of said sets of redundant write global data line pairs (29), a corresponding one of said write fuses (25, 32, 87, and 88), and to said comparator means (45), for either writing data onto said write global data line pairs (37, 42, 43, and 41), or for writing data onto said redundant write global data line pairs (29) selectively in response to said comparator means (45) detecting a defective column when the memory (20) is in the write mode; a plurality of read fuses (59, 80, 85, and 86) for selecting which of said redundant columns is to replace a defective column when the memory (20) is in the read mode; and a plurality of read portions (50A, 50B, 50C, and 50D), each coupled to a corresponding one of said sets of read global data line pairs (29), a corresponding one of said redundant read global data line pairs (44), a corresponding one of said read fuses (59, 80, 85, and 86) and to said comparator means (45) for either reading data from said read global data line pairs (29), or for reading data from said redundant read global data line pairs (44) selectively in response to said comparator means (45) detecting a defective column when the memory (20) is in the read mode.

Claim 7

The memory of Claim 6, wherein each write fuse (25, 32, 87, and 88) provides a DC logic signal to a write portion (30A, 30B, 30C, and 30D) corresponding thereto when a fusible link (101) in said write fuse (25, 32, 87, and 88) is blown to indicate which redundant column is to replace a defective column.

Claim 8

The memory of Claim 7, further comprising a plurality of redundant write generators (31), each coupled to a corresponding one of said write portions (30A, 30B, 30C, and 30D) and to said comparator means (45), for receiving said DC logic signal and providing a control signal to deselect a defective column to prevent data from being written onto the defective column when the memory (20) is in the write mode.

Claim 9

The memory of Claim 6, wherein each read fuse (59, 80, 85, and 86) provides a DC logic signal to a read portion (50A, 50B, 50C, and 50D) corresponding thereto when a fusible link (101) in said read fuse (59, 80, 85, and 86) is blown to indicate which redundant column is to replace a defective column.

Claim 10

The memory of Claim 9, further comprising a plurality of redundant read generators (60, 61, 81, and 82), each coupled to a corresponding one of said read portions (50A, 50B, 50C, and 50D) and to said comparator means (45), for receiving said DC logic signal and providing a control signal to deselect a defective column to prevent data from being read from the defective column when the memory is in read the mode.