EP0557253A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
VDMOS transistor with improved breakdown characteristics
Assignee: STMicroelectronics SRL
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Filing: 1993-02-11
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Granted: —
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Expires: 2013-02-11
Abstract
Abstract The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.
Inventors
- 👤 Claudio Contiero
- 👤 Maria Paola Galbiati
- 👤 Lucia Zullino
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 09:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/663; H10D30/668; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/126
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
72 words
An VDMOS transistor comprising at least a matrix of source cells a dielectric, field-isolation, layer alongside said matrix and a field-plate structure overlying an edge portion of said field-isolation layer facing peripheral cells of said matrix of source cells, characterized by comprising a field-isolation diffusion under said dielectric field-isolation layer, along the edge facing said peripheral cells and an electrical connection between said field-isolation diffusion and a source region of the transistor.
Claim 2
Dependent Claim
34 words
A VDMOS transistor as defined in claim 1, wherein said electrical connection is constituted by a projection of a body region of at least one of said peripheral cells that intersects said field-isolation diffusion.
Claim 3
Dependent Claim
35 words
A VDMOS transistor as defined in claim 1, characterized by comprising a plurality of alternated matrices of source cells and drain-connection diffusions separated by a strip of said dielectric field-isolation layer forming an inter-digitated structure.
Claim 4
Dependent Claim
26 words
A VDMOS transistor as defined in claim 1, characterized by being an n-channel transistor, having P-body regions formed in an epitaxial layer having an N-type conductivity.
Claim 5
Dependent Claim
46 words
A VDMOS transistor as defined in claim 4, wherein a P-body region of at least a peripheral source cell facing the edge of said dielectric field-isolation layer overlying a P-field isolation diffusion, extends as far as intersecting said P-field isolation diffusion for establishing said electrical connection.
Claim 6
Dependent Claim
124 words
An integrated VDMOS transistor comprising at least a matrix of source cells and a drain-connection diffusion, a field-isolation diffusion, under a strip of a field-isolation dielectric layer separating said matrix of cells from said drain-connection diffusion and a biplanar field-plate overlaying an edge portion of said dielectric field-isolation layer facing peripheral cells of said matrix, and wherein said field-isolation diffusion under said edge portion of the dielectric field-isolation layer, topped by said field-plate, is electrically connected to a source region of the transistor through a projection of a body region of at least one of said peripheral source cells of said matrix extending toward the edge of said dielectric field-isolation layer and intersecting said field-isolation diffusion present under the edge of said field-isolation layer.
Claim 7
Independent Claim
54 words
A method for increasing the breakdown voltage of a VDMOS transistor comprising at least a matrix of source cells and a dielectric field-isolation layer characterized by the fact that comprises forming a field-isolation diffusion under said field-isolation layer and tying the electrical potential of said field-isolation diffusion to the source potential of the transistor.
Claim 8
Independent Claim
58 words
A method for increasing the breakdown voltage of an integrated VDMOS transistor comprising at least a matrix of source cells and a drain-connection diffusion, separated by a strip of dielectric field-isolation layer and which comprises forming a field-isolation diffusion under said strip of field-isolation layer and electrically connecting said field-isolation diffusion to a source region of the transistor.
Claim 9
Independent Claim
51 words
A method for increasing the breakdown voltage of an integrated VDMOS transistor comprising at least a matrix of source cells and a dielectric field-isolation layer formed over a field-isolation diffusion, characterized by the fact that comprises tying the electrical potential of said field-isolation diffusion to the source potential of the transistor.
References Cited (Backward Citations)
No citation records indexed.
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