EP0554626A2
Expired / Lapsed
EP
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Time division multiplexer chip in a voice processing system
Assignee: Dictaphone Corp
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Filing: 1992-12-30
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Granted: —
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Expires: 2012-12-30
Abstract
Abstract A time division multiplexer (TDM) chip having particular application in a digital voice processing system wherein voice processing functions are run in software. The TDM chip has a pair of RAMs (42a,42b) which are in communication with a bus (32) and at least one interface (30) that provides communication with other devices. An bank switch (86) controls the RAMs so that their communication with the bus and the interface alternates, i.e. while the first RAM (42a) is in communication with the interface the other RAM (42b) is in communication with the bus (32). After a determined period the communications are reversed. This scheme provides faster processing and more efficient use of the components. Including is a provision for allowing multiple interfaces to communicate with the RAM alternatively in a time shared manner.
Inventors
- 👤 Daniel F. Daly
- 👤 John J. Dwyer
- 👤 Salvatore J. Morlando
- 👤 Mark Sekas
- 👤 Shamla V. Sharma
- 👤 Judith Dixon-Otton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 10:24
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0421; H04M; H04M3/00; H04M3/42; H04M3/487; H04M3/50; H04M3/53; H04M3/533
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
113 words
A time division multiplexor chip, comprising: at least one first interface, a pair of RAMs in alternate communication with said at least one first interface, a second interface in alternate communication with said pair of RAMs, an address generator in alternate communication with said pair of RAMs, a bank switch unit in communication with said pair of RAMs for switching communication of each RAM of said pair of RAMs alternately with said at least one interface and said second interface, and a clock in communication with said bank switch unit for providing a frame synch clock to said bank switch unit whereby upon each frame boundary said pair of RAMs will be switched.
Claim 2
Dependent Claim
51 words
The time division multiplexer chip of Claim 1 wherein said at least one first interface is a plurality of interfaces and further comprising an interrupt unit in communication with said plurality of first interfaces for controlling which of said first interfaces is to be in communication with one of said RAMs.
Claim 3
Dependent Claim
34 words
The time division multiplexel chip of Claim 2 further comprising a failure detector in communication with said second interface to determine if data sent from said second interface is data received from a RAM.
Claim 4
Dependent Claim
21 words
The time division multiplexer of Claim 3 further comprising a clock failure detector for determining if said clock has a failure.
Claim 5
Dependent Claim
144 words
A time division multiplexer chip for use in a voice processing system comprising: a pair of first interfaces, a pair of RAMs in alternate individual, selective communication with said pair of first interfaces, an arbitration unit in communication with said pair of first interfaces to control which of said interfaces is to communicate with a RAM, a second interface in alternate individual selective communication with said pair of RAMs, a bank switching unit in communication with said pair of RAMs for switching communication of each of said RAMs between said pair of first interfaces and second interface, and a clock in communication with said arbitration unit and with said bank switching unit for providing a frame synch clock to said bank switch unit whereby upon each frame boundary said pair of RAMs switch communication between said first pair of interface and said second interface.
Claim 6
Dependent Claim
69 words
The time divide multiplexor chip of Claim 4 further comprising a second pair of first interfaces each of which is in individual selective communication with said pair of RAMs, a second arbitration unit in communication with said clock and with said second pair of first interfaces for controlling which of said second pair of first interfaces is to be in communication with one or the other of said RAMs.
Claim 7
Dependent Claim
26 words
The time division multiplexer chip of Claim 6 further including a time slot address generator in communication with said pair of RAMs and with said clock.
Claim 8
Dependent Claim
39 words
The time division multiplexer chip of Claim 7 further comprising an interrupt unit in communication with said time slot address generator for controlling the activities of processors which are attached to said first and second pair of said interfaces.
Claim 9
Dependent Claim
41 words
The time division multiplexor chip of Claim 8 further comprising a failure detector in communication with said second interface to determine if data sent from said second interface is the same data received by said interface from one of said RAMs.
Claim 10
Dependent Claim
63 words
A time division multiplexor chip comprising: a pair of RAMs, first and second interfaces each having selective communication means for alternately communication on a one to one basis with said first and second interfaces, a bank switch unit in communication with said RAMs for switching communication of each RAMs with said interfaces, and a clock in communication with said time bank switch unit.
Claim 11
Dependent Claim
34 words
The time divide multiplexor chip of Claim 10 further comprising a processor in communication with said first interface, an interrupt unit in communication with said interfaces for providing an interrupt signal to said processor.
Claim 12
Dependent Claim
47 words
The time division multiplexor chip of Claim 10 further comprising a failure detector in communication with one of said second interface to determine if data received by said one second interface from one of said RAMs is the same data output by said one of said interfaces.
Claim 13
Independent Claim
76 words
A method of processing voice data, the steps comprising: a. receiving first voice data from a first interface and writing said first voice data into a first RAM, b. receiving second voice data from a second interface and writing said second voice data into a second RAM, c. transmitting said first voice data in first RAM to said second RAM, and d. transmitting said second voice data of one said second RAM to said first RAM.
Claim 14
Independent Claim
149 words
A method of processing voice data comprising the steps of:- a. transmitting voice data to a first interface, b. connecting the first interface with a first RAM, c. transferring voice data from said first interface to said first RAM, d. transmitting voice data to a second interface, e. connecting the second interface to a second RAM, f. transferring voice data from said second interface to the second RAM, g. discontinuing connection between said first interface and said first RAM, h. discontinuing connection between said second interface and said second RAM, i. connecting said first interface to said second RAM, j. transferring voice data from said second RAM to said first interface, k. outputting voice data from said first interface, 1. connecting said second interface with said first RAM, m. transferring voice data from said first RAM to said second interface, and n. outputting voice data from said second interface,
Claim 15
Dependent Claim
34 words
The method of Claim 13 further including the step of determining if the data output from said first interface is the same as the data received by said first interface from said second RAM.
References Cited (Backward Citations)
No citation records indexed.
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