EP0549055A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device
Assignee: FASELEC AG
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Filing: 1992-12-16
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Granted: —
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Expires: 2012-12-16
Abstract
Abstract A method of manufacturing a semiconductor device comprising a field effect transistor and a device manufactured by this method in which a high packing density can be realised. The field effect transistor comprises a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41). At least the source (32,42) or the drain (33,43) of the transistor is provided with an electrical connection (20) which makes contact through a contact window (19) in a further insulating layer (16). Due to the complete insulation of the gate electrode (31,41), said contact window (19) is allowed to overlap the associated gate electrode (31,41), so no alignment tolerances need be taken into account relative to the gate electrode (31,41) for forming this window (19).
Inventors
- 👤 José Solo de Zaldivar
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 15:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
277 words
A method of manufacturing a semiconductor device whereby a field effect transistor is provided at a surface of a semiconductor body, which transistor comprises a source and a drain of a first conductivity type mutually separated by a channel region of a second, opposite conductivity type, and comprising a gate electrode which is insulated from the channel region by a first insulating layer, whereby the first insulating layer is provided on the surface of the semiconductor body and is covered with a conductive layer, an etching mask is provided and a gate electrode is etched from the conductive layer under masking of this mask, exposed portions of the gate electrode are covered with insulating material, the semiconductor body is doped with an impurity on both sides of the gate electrode for forming the source and drain, the assembly is covered with a further insulating layer which at the area of at least either the source or the drain is provided with a contact window which lies partly above the gate electrode, and an electrical connection is provided in the contact window, characterized in that the conductive layer is covered with a second insulating layer before the etching mask is provided, in that the second insulating layer is etched into a pattern under masking of the etching mask, in that after the formation of the gate electrode a third insulating layer is deposited on the assembly and subsequently anisotropically etched in such a manner that afterwards a portion thereof remains along the edge of the gate electrode, and in that via the contact window an electrical connection is provided which extends at least partly over the gate electrode.
Claim 2
Dependent Claim
49 words
A method as claimed in Claim 1, characterized in that, before the etching mask is provided, the second insulating layer is locally removed from the conductive layer and in that a contact region of the conductive layer thus exposed is covered at least in part by the etching mask.
Claim 3
Dependent Claim
41 words
A method as claimed in Claim 2, characterized in that the further insulating layer is also provided with a contact window at the area of the contact region of the conductive layer and in that an electrical connection is provided therein.
Claim 4
Dependent Claim
56 words
A method as claimed in Claim 3, characterized in that at least the contact region of the conductive layer is covered with a dielectric, in that the dielectric is exposed in the contact window, and in that an electrical connection is provided via the contact window on the dielectric so as to form a capacitance electrode.
Claim 5
Independent Claim
106 words
A method as claimed in any one of the preceding Claims, characterized in that, before the third insulating layer is provided, the semiconductor body on either side of the gate electrode is doped with an impurity of the first conductivity type so as to form a first, comparatively weakly doped portion of the source and the drain, and in that, after the portion along the gate electrode has been formed from the third insulating layer, the semiconductor body is once more doped with an impurity of the first conductivity type so as to form a second, comparatively heavily doped portion of the source and the drain.
Claim 6
Independent Claim
26 words
A method as claimed in any one of the preceding Claims, characterized in that the second insulating layer comprises silicon oxide and is provided by deposition.
Claim 7
Independent Claim
44 words
A method as claimed in any one of the preceding Claims, characterized in that, after the third insulating layer has been etched back anisotropically, the entire assembly is covered with an etch stop layer relative to which the further insulating layer is selectively etchable.
Claim 8
Dependent Claim
26 words
A method as claimed in Claim 7, characterized in that the etch stop layer comprises a material from the group of silicon nitride and aluminium oxide.
Claim 9
Dependent Claim
66 words
A method as claimed in Claim 7 or 8, characterized in that a layer of flow glass is used for the further insulating layer, in that subsequently said contact window is provided therein and a heat treatment is carried out whereby the further insulating layer flows out, and in that the etch stop layer is not removed from the contact window until after the heat treatment.
Claim 10
Dependent Claim
184 words
A semiconductor device comprising a semiconductor body provided with a field effect transistor with a source and a drain of a first conductivity type mutually separated by a channel region of a second, opposite conductivity type, and with a gate electrode which is separated from the channel region by a first insulating layer, the source and drain both adjoining the channel region with a comparatively weakly doped portion and the entire assembly being covered by a further insulating layer which at the area of at least the source or the drain is provided with a contact window in which an electrical connection is provided, characterized in that in that the gate electrode is covered with a second insulating layer under the further insulating layer, in that the second insulating layer and the gate electrode have at least substantially identical patterns at least at the area of the channel region, in that the contact window lies partly above the gate electrode and in that the electrical connection extends partly over the gate electrode and is electrically insulated therefrom by at least the second insulating layer.
Claim 11
Dependent Claim
56 words
A semiconductor device as claimed in Claim 10, characterized in that the second insulating layer leaves the gate electrode uncovered at the area of a contact region thereof and in that the further insulating layer is provided with a contact window at the area of the contact region, in which window an electrical connection is provided.
Claim 12
Dependent Claim
95 words
A semiconductor device as claimed in Claim 10, characterized in that a first capacitance electrode of at least substantially the same composition and thickness as the gate electrode is provided on the first insulating layer, in that the second insulating layer leaves the first capacitance electrode at least partly uncovered, in that the further insulating layer is provided with a contact window at the area of the first capacitance electrode, and in that a second capacitance electrode is provided in the contact window, the said two capacitance electrodes being mutually separated by a capacitor dielectric.
Claim 13
Dependent Claim
40 words
A semiconductor device as claimed in Claim 12, characterized in that an dielectric layer relative to which the further insulating layer is selectively etchable lies below the further insulating layer, which dielectric layer at least partly forms the capacitor dielectric.
References Cited (Backward Citations)
No citation records indexed.
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