Clocking mechanism for delay, short path and stuck-at testing

Claim 1

A digital logic circuit for testing a logic circuit block which has a set of input signal lines and a set of output signal lines, said circuit for testing comprising: a first shift register latch scan string having a plurality of latch pairs with each one of said pairs including a master latch and a slave latch and with output signal lines of said slave latches being connected to the input signal lines of said logic circuit block and also with output signal lines of said slave latches being connected to a single subsequent master latches in these scan strings so as to form a shift register; a second set of latch pairs with each one of said second set including a master and a slave latch with said output signals of said logic circuit block being connected to input signal lines of said master latches in said second set of latch pairs; first clock means (A and B) for shifting signal values along said scan string one latch at a time; second clock means (C1) for controlling the loading of output signal values from said logic circuit block into said master latches in said second set of latch pairs; third clock means (C2) for transferring signal values from said master latches to the respective slave latches in said shift register latch scan string without transferring signal values between said latch pairs therein; means for suppressing a single pulse from said second clock means, whereby it is assured that a pulse from said third clock means occurs earlier than a pulse from said second clock means.

Claim 3

A method for testing a logic block, said method comprising the steps of: performing a skewed load of mixed binary data into a shift register latch scan string; exciting said logic block with transition signals from said shift register latch; capturing the response of said logic block to said transition signal excitation in a set of output latches.