BiCMOS bus interface output driver compatible with a mixed voltage system environment

Claim 2

A low voltage output driver operating between a supply voltage source and ground, comprising: a buffer stage comprising an input and an output; a pull-up transistor coupled to said output; blocking circuitry coupled to said pull-up transistor and said buffer stage for blocking current flow from said output to said supply voltage source, such that said output driver is compatible with a mixed voltage signal environment.

Claim 3

The output driver of Claim 1 wherein said buffer stage includes CMOS and bipolar devices, and said pull-up transistor comprises a p-channel field effect transistor.

Claim 4

The output driver of Claim 1 or Claim 2, wherein said pull-up transistor includes a first substrate, gate, drain and source and wherein said blocking circuitry comprises a first blocking diode with a first cathode and a first anode, said first cathode coupled to said first substrate, and said first anode coupled to said supply voltage source.

Claim 5

The output driver of Claim 3, wherein said blocking circuitry further comprises a first clamping transistor coupled to said pull-up transistor and said buffer stage and operable to clamp said output to said first gate.

Claim 6

The output driver of Claim 4, wherein said first clamping transistor comprises a second substrate, a second gate, a second drain, and a second source, said second subsstrate being coupled to said first cathode, said second gate being coupled to said supply voltage source, said second drain coupled to said output, and said second source coupled to said first gate.

Claim 7

The output driver of any preceding claim, wherein said blocking circuitry further comprises a second blocking diode comprising a second cathode and a second anode, said second cathode coupled to said buffer stage and said second anode coupled to said supply voltage source.

Claim 8

The output driver of Claim 6 wherein said buffer stage comprises an upper CMOS inverter, said second diode coupled between said upper CMOS inverter and said supply voltage source.

Claim 9

The output driver of Claim 3 or any of claims 4 to 7 when dependant on claim 3, wherein said blocking circuitry further comprises a second clamping transistor coupled to said pull-up transistor and said buffer stage, and operable to clamp said output to said first gate at a lower output voltage than said first clamping transistor.

Claim 10

The output driver of Claim 8, wherein said blocking circuitry further comprises: a biasing diode comprising a third cathode and a third anode, said third anode coupled to said supply voltage source; said second clamping transistor comprises a third substrate, a third gate, a third source, and a third drain, said third substrate coupled to said first cathode, said third gate coupled to said third cathode, said third source coupled to said first gate, and said third drain coupled to said output; and a first biasing resistor coupled to said ground and said third cathode.

Claim 11

The output driver of claim 4 or any of claims 5 to 9 when dependant on claim 4, wherein the or each clamping transistor comprises a p-channel field effect transistor.

Claim 12

The output driver of Claim 4 to 10 or any of claims to when dependant on claim 3, wherein the or each diode comprises a Schottky diode.

Claim 15

The method of Claim 12 wherein a pull-up transistor is coupled to the output signals, said step of blocking comprising blocking current flow from the mixed voltage signal environment through the substrate of the pull-up transistor.

Claim 16

The method of Claim 12 or Claim 13, wherein said step of blocking further comprises clamping the gate of the pull-up transistor to the mixed voltage signal environment.

Claim 18

The method of Claim 15 and further comprising the step of clamping the gate of the pull-up transistor to the mixed voltage signal environment through a second clamping transistor.