EP0544315A2
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Maximum likelihood sequence estimation apparatus
Assignee: NEC Corp
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Filing: 1992-11-26
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Granted: —
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Expires: 2012-11-26
Abstract
Abstract The maximum likelihood sequence estimation apparatus decodes a digital data signal. The apparatus comprises sampling means to perform sampling and output a received signal by sampling pulses having a constant time interval T and N different sampling phases, operation means to operate branch metric of the received signal sampled by the N different sampling phases, and means to perform the maximum likelihood sequence estimation of the branch metric. <IMAGE>
Inventors
- 👤 Kazuhiro C/O Nec Corporation Okanoue
- 👤 Akihisa C/O Nec Corporation Ushirokawa
- 👤 Yukitsuna C/O Nec Corporation Furuya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 19:57
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; H; H03; H03M; H03M13/00; H03M13/37; H03M13/39; H03M13/41; H04; H04L; H04L1/00; H04L1/02; H04L1/06; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03178; H04L25/03184
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
86 words
A maximum likelihood sequence estimation apparatus to decode a digital data signal, comprising: (a) sampling and outputting means for sampling a received signal in N (N being an integer larger than 1) different sampling phases using a sampling pulse having N different phases each having a constant time interval T; (b) calculation means for receiving the received signal sampled in the N different sampling phases to calculate the branch metric; and (c) means to receive the branch metric for estimation of the maximum likelihood sequence estimation.
Claim 2
Dependent Claim
116 words
A maximum likelihood sequence estimation apparatus of claim 1 characterized in that said means to calculate the branch metric comprises: (a) means to estimate the channel impulse response from the input signals derived from sampling in said different sampling phases for outputting the estimation value of the channel impulse response; (b) means to output the partial branch metric by obtaining the branch metric for each input signal in accordance with the output signal sampled in said N different sampling phases and the estimated value of the channel impulse response for each output signal sampled in said N different sampling phases; and (c) means to output the addition of said partial branch metrics as the branch metric.
Claim 3
Dependent Claim
88 words
A maximum likelihood sequence estimation apparatus of claim 1 or 2 characterized in that said sampling and outputting means for sampling the received signal in N different sampling phases using a sampling pulse having N different phases and a constant interval T comprises: (a) means to generate a sampling pulse having a frequency 1/NT; (b) means to divide said sampling pulse by 1/N and output N sampling pulse trains of N different phases; and (c) means to perform sampling the received signal by said N sampling pulse trains.
Claim 4
Dependent Claim
163 words
A maximum likelihood sequence estimation apparatus to decode a digital data signal, comprising: (a) pulse generator circuits to generate N (N being an integer larger than 1) different sampling pulses each having a constant time interval T; (b) N A-D converters to perform sampling and digitizing the received signal by sampling whenever said sampling pulses from said N pulse generator circuits; (c) N channel impulse response estimation circuits to estimate and output the channel impulse response for each input from said N A-D converters; (d) N branch metric calculation circuits to calculate and output the branch metric for each output from each of said N channel impulse response estimation circuits and each of said N A-D converters; (e) a branch metric composite circuit to receive the output from each of said N branch metric calculation circuits for outputting the composite branch metric by composing the branch metrics; and (f) a Viterbi processor to receive the composite branch metric for outputting the decision result.
Claim 5
Dependent Claim
195 words
A maximum likelihood sequence estimation apparatus to decode a digital data signal, comprising: (a) a pulse generator for generating a sampling pulse having a constant time interval T; (b) N (N being an integer larger than 1) delay circuit to delay the sampling pulse by kT/N (k = 0, 1, 2 ..., N-1); (c) N A-D converters for sampling and digitizing the received signal whenever the sampling pulse from said N delay circuits is applied; (d) N channel impulse response estimation circuits to receive the output from each of said N A-D converters and the decision result for estimating and outputting the channel impulse response for the input signal; (e) N branch metric calculation circuits to receive the output from each of said N channel impulse response estimation circuits and the output from each of said N A-D converters for calculating and outputting the branch metric for each input; (f) a branch metric composite circuit to receive the output from each of said N branch metric calculation circuits for composing the branch metrics and outputting the composed branch metric; and (g) a Viterbi processor to receive the composed branch metric for outputting the decision result.
Claim 6
Dependent Claim
207 words
A maximum likelihood sequence estimation apparatus to decode a digital data signal, comprising: (a) a pulse generator for generating a sampling pulse having a constant time interval T; (b) N (N being an integer larger than 1) delay circuit to delay the sampling pulse by kT/N (k = 0, 1, 2, ..., N-1); (c) N A-D converters for sampling and digitizing the received signal whenever the sampling pulse from said N delay circuits is applied; (d) N channel impulse response estimation circuits to receive the output from each of said N A-D converters and the decision result for estimating and outputting the channel impulse response for the input signal and the respective estimation path information; (e) N branch metric calculation circuits to receive the output from each of said N channel impulse response estimation circuits and the output from each of said N A-D converters for calculating and outputting the branch metric for each input; (f) a branch metric composite circuit to receive the output and the respective estimation path information from each of said N branch metric calculation circuits for composing the branch metrics and outputting the composed branch metric; and (g) a Viterbi processor to receive the composed branch metric for outputting the decision result.
Claim 7
Dependent Claim
46 words
A maximum likelihood sequence estimation apparatus of claim 4 or 5 wherein said branch metric composite circuit comprises an adder to receive as an input signal the output from each of said N branch metric calculation circuits for providing the output by adding the input signals.
Claim 8
Independent Claim
29 words
An apparatus of any one of claims 4 to 7 wherein said pulse generator circuit generates the sampling pulse at the symbol time interval of the digital data signal.
Claim 9
Independent Claim
172 words
An apparatus of any one of claims 5 to 8 characterized in that each of said N channel impulse response estimation circuits comprises: (a) an M-tapped transversal filter to receive the decision result as an input for outputting the filtering result and the time sequence of the decision results by filtering the time sequence of the decision results inputted at time interval K-M through K with the channel impulse response estimation vector Hk at time k as the tap factor; (b) a delay circuit to receive the output from each of said A-D converters as an input for delaying the input signal by the decoding delay time caused by said Viterbi processor; (c) a subtraction circuit to detect and output the error signal between the output from said delay circuit and the filtering result; and (d) an adaptive control processor to receive the time sequence of the decision results and the error signal for updating the channel impulse response estimation value to be supplied to said transversal filter and the output terminal.
Claim 10
Independent Claim
184 words
An apparatus of any one of claims 6 to 9 characterized in that each of said N channel impulse response estimation circuits comprising: (a) an M-tapped transversal filter to receive the decision result as an input for outputting the filtering result and the time sequence of the decision results by filtering the time sequence of the decision results inputted at time interval K-M through K with the channel impulse response estimation vector H(k) at time k as the tap factor; (b) delay circuits to receive the output from the respective A-D converters for delaying the input signal by the time equal to the decoder delay caused in said Viterbi processor; (c) a subtraction circuit to detect and output the error signal between the output from said delay circuits and the filtering result; (d) an adaptive control processor to receive the time sequence of the decision result and the error signal for updating the channel impulse response estimation value to output to both of said transversal filter and the output terminal; and (e) a terminal to output the error signal as the estimation process information.
References Cited (Backward Citations)
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