EP0543197A2
Expired / Lapsed
EP
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Multiple serial access memory for use in feedback systems such as motion compensated television
Assignee: Arris Technology Inc
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Filing: 1992-10-31
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Granted: —
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Expires: 2012-10-31
Abstract
Abstract A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.
Inventors
- 👤 Paul Shen
- 👤 Woo H. Paik
- 👤 Edward A. Krause
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; G06; G06T; G06T1/00; G06T1/60; G11C7/1015; G11C7/1036; H04N19/43; H04N19/433; H04N19/50; H04N19/503; H04N19/51; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
79 words
A multiple serial access memory comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom.
Claim 2
Dependent Claim
32 words
A memory in accordance with claim 1 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.
Claim 3
Dependent Claim
95 words
A memory in accordance with claim 1 or 2 wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from said serial output port.
Claim 4
Dependent Claim
142 words
In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising: a dynamic random access memory array; means for addressing said array to input data thereto and output data therefrom; means for outputting rows of data from said array in response to address signals provided by said addressing means; a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and means for clocking said serial output ports to output latched data therefrom; wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array.
Claim 5
Dependent Claim
32 words
Television apparatus in accordance with claim 4 further comprising: timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.
Claim 6
Dependent Claim
97 words
Television apparatus in accordance with one of claims 4 or 5 wherein each of said serial output ports comprises: a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from said serial output port.
Claim 7
Dependent Claim
60 words
Television apparatus in accordance with one of claims 4 to 6 wherein: said working data is accessed from the array by its respective serial output port in one of a field format and frame format; and said display data is accessed from the array by its respective serial output port in the other of said field format and frame format.
Claim 8
Dependent Claim
50 words
Television apparatus in accordance with one of claims 4 to 6 wherein: said working data is accessed from the array by its respective serial output port in a block format; and said display data is accessed from the array by its respective serial output port in a television line format.
Claim 9
Dependent Claim
114 words
Television apparatus in accordance with one of claims 4 to 8 wherein: said display data comprises pixel data for a current video frame; said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal; said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.
Claim 10
Independent Claim
159 words
A method for storing video data for use by a motion compensator that estimates motion over a maximum horizontal displacement DX and a maximum vertical displacement DY , comprising the steps of: providing a frame store memory for storing N + K lines of video data, where N is the number of lines in a video frame and K is at least equal to the number of lines corresponding to the vertical displacement DY ; and filling said frame store memory with video data from successive video frames on a revolving basis, wherein N consecutive lines of a second video frame are written into said memory following the last line of a first video frame, such that the first video frame is overwritten by the second video frame on a first-in first-out basis, with the last K lines of the first video frame remaining in said memory once the full second video frame has been written into said memory.
References Cited (Backward Citations)
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