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EP0541303A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Optical circulating shift register

Assignee: AT&T Inc
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Filing: 1992-10-30
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Granted: —
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Expires: 2012-10-30
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Abstract

Abstract An all-optical circulating shift register (100) encodes a received optical clock signal (at SI) with a value derived from an encoded optical signal received at a control port (CTLI) thereof. A data input (at 150) to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port (SRO), is coupled back to the control port (CTLI). The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch (110) having a feedback path (120) coupled between an output port (3) and a control port (CTLI) of the Sagnac switch.

Inventors

  • 👤 Hercules Avramopoulos
  • 👤 M.Christina Gabriel
  • 👤 Alan Huang
  • 👤 Norman Ashton Whitaker, Jr.

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-23 21:14
CPC Classifications
G; G11; G11C; G11C21/00; G02; G02B; G02B6/00; G02B6/24; G02B6/26; G02B6/28; G02B6/2804; G02B6/2821; G02B6/2843

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 96 words
A circulating shift (100) register arrangement CHARACTERIZED BY: encoding means utilizing all-optical interaction, including means (SI) for receiving an optical clock signal, control means (CTLI) for receiving an encoded optical signal, means (SO) for outputting an encoded optical clock signal, wherein said encoding means encodes the received clock signal with a value derived from said encoded signal, and wherein a signal delay caused by said encoding means from said control means to said output means is a prespecified time interval; means 120 for coupling the encoded clock signal from said output means to said control means.
Claim 2
Dependent Claim 24 words
The shift register arrangement of claim 1 further comprising means (C2) for entering data into the shift register to modify the encoded clock signal.
Claim 3
Dependent Claim 23 words
The shift register arrangement of claim 1 further comprising means (180) for modulating said clock signal in response to a received data signal.
Claim 4
Dependent Claim 27 words
The shift register arrangement of claim 1 wherein the coupling means includes means (191) for modulating the encoded clock signal in response to a received data signal.
Claim 5
Dependent Claim 28 words
The shift register arrangement of claim 1 wherein the time interval between two or more pulses of said clock signal are substantially equal to said prespecified time interval.
Claim 6
Dependent Claim 29 words
The shift register arrangement of claim 1 wherein said encoding means includes a second control means (SO) for inputting a received data signal for modulating the encoded clock signal.
Claim 7
Dependent Claim 205 words
The shift register arrangement of claim 1 wherein said encoding means includes a Sagnac switch (110) including an optical transmission medium (10) having a controllable propagation speed characteristic; input port means (SI) for serially injecting said clock signal into said medium to develop an interacting signal that travels in said medium in one direction and a reference signal that travels in said medium in the opposite direction; control port means (CTLI) for injecting a control signal into said medium, said control signal travels through said medium in the direction of said interacting signal, with the timing of said control signal, in relation to said interacting signal, controlled to traverse the control signal by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means (20) for generating a combined signal by combining said interacting signal with said reference signal after said signals have traveled through said medium; output port means (SO) for outputting said combined signal; and wherein said receiving means is coupled to said input port of said Sagnac switch, said control means is coupled to said control port of said Sagnac switch, and said coupling means couples an output port of said Sagnac switch to said control port.
Claim 8
Dependent Claim 17 words
The shift register arrangement of claim 7 wherein said medium includes an even number of crossed-axis splices.
Claim 9
Dependent Claim 22 words
The shift register arrangement of claim 7 wherein said output port outputs a combined signal in the absence of said control signal.
Claim 10
Dependent Claim 21 words
The shift register arrangement of claim 7 wherein said output port outputs a combined signal when said control signal is present.
Claim 11
Dependent Claim 25 words
The shift register arrangement of claim 1 wherein said output port alternately outputs said encoded clock signal and an inverse of said encoded clock signal.
Claim 12
Dependent Claim 23 words
The shift register arrangement of claim 1 wherein said coupling means includes a feedback path having an optical amplifier (160) connected serially therein.
Claim 13
Dependent Claim 25 words
The shift register arrangement of claim 1 wherein said coupling means includes a feedback path causing a predetermined time delay to said encoded clock signal.
Claim 14
Dependent Claim 54 words
The shift register arrangement of claim 1, further comprising means (C3) for inputting a probe signal to said encoding means, means for outputting an encoded probe signal from said encoding means, and wherein said encoding means encodes the probe signal with a value derived from said encoded signal to produce said encoded probe signal.
Claim 15
Dependent Claim 230 words
An optical circuit arrangement CHARACTERIZED BY an optical transmission medium (10) including controllable propagation speed material; input port means (SI) for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means (CTLI) for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means (C2) for coupling encoded optical data pulses received during a first frame interval, into said control port means; means (20) for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be a replica of said first frame of received encoded data pulses; means (120) for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulses being used by said encoding means to encode a second frame of clock pulses; and means (50) for outputting said encoded clock pulses.
Claim 16
Dependent Claim 240 words
An optical circuit arrangement CHARACTERIZED BY an optical transmission medium including controllable propagation speed material (10); input port means (SI) for injecting optical clock pulses into said medium to develop, for each clock pulse, an interacting signal that travels in said medium in one direction and an associated reference signal that travels in said medium in the opposite direction; control port means (CTLI) for injecting control pulses into said medium, each control pulse travels through said medium in the direction of said interacting signal medium in the direction of said interacting signal, with the timing of a control pulse, in relation to said interacting signal, controlled to traverse the control pulse by the interacting signal while the interacting signal is traveling through said controllable propagation speed material; means (C2) for coupling encoded optical data pulses, received during a first frame interval, into said control port means; means (20) for encoding each clock pulse, by combining said interacting signal with said associated reference signal after said signals have traveled through said medium, a first frame interval of clock pulses being encoded to be an inverse replica of said first frame of received encoded data pulses; means (120) for coupling said first frame of encoded clock pulses into said control port means, said first frame of encoded clock pulse being used by said encoding means to encode a second frame of clock pulses; and means (SO) for outputting said encoded clock pulses.

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