EP0540286A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

High-frequency power divider and combiner

Assignee: NTT Docomo Inc

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Filing: 1992-10-27

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Granted: —

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Expires: 2012-10-27

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Abstract

Abstract In a power amplifying apparatus which has a high-frequency power divider and combiner and two to four parallel-operated power amplifiers, in which a change is made in the number of the parallel-operated power amplifiers so as to adjust output power, there are provided a power dividing circuit D₁ having a transmission line Wd₅₁ serving as an impedance transformer set in such a manner that the power loss is minimized by assigning an intermediate number 3 between 2 and 4 both of which indicate the number of divisions, and having four output terminals, and a power combining circuit S₁ having a transmission line Ws₅₁ serving as an impedance transformer set in such a manner that the power loss is minimized by assigning the intermediate number 3 indicative of the number of combinations, and having four input terminals.

Inventors

👤 Hironori Sakamoto
👤 Akira Ito
👤 Toshio Nojima

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-07 13:02

CPC Classifications

H; H01; H01P; H01P5/00; H01P5/12; H01P5/02; H03; H03F; H03F3/00; H03F3/60; H03F3/602

Claims Analysis

Total Claims: 2

Claim 1

Independent Claim 159 words

A high-frequency power divider and combiner for use in a power amplifying apparatus which includes a plurality of power amplifiers (A₁, A₂, A₃, A₄) parallel-operated in a range between M and N (where M and N are positive integers and M<N) both indicative of the number of the power amplifiers and which makes a change in the number of the parallel-operated power amplifiers to thereby,control output power, said high-frequency power divider and combiner comprising: a power dividing circuit (D₁) having an impedance transformer (Wd₅₁) set in such a manner that the power loss is minimized by assigning an intermediate number K (positive integer) between M and N both of which indicate the number of divisions and having N output terminals; and a power combining circuit (S₁) having an impedance transformer (Ws₅₁) set in such a manner that the power loss is minimized by assigning said intermediate number K corresponding to the number of combinations and having N input terminals.

Claim 2

Dependent Claim 95 words

A high-frequency power divider and combiner according to claim 1, wherein a plurality of transmission lines (Ws₂₁, Ws₂₂, Ws₂₃, Ws₂₄) serving as an impedance transformer each having a predetermined impedance and a predetermined line length are connected from respective input terminals of said combiner, the impedance transformation of said impedance transformer is separately made between respective transmission lines electrically connected to the corresponding transmission lines (Ws₁₁, Ws₁₂, Ws₁₃, Ws₁₄) and a combining point (P) and an impedance transformer (Ws₅₂; Ws₅₃) is connected to said combining point (P) so as to carry out the impedance transformation.

References Cited (Backward Citations)

US3522550A Cited

US4893093A Cited

US4965530A Cited

US5032798A Cited

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