Pseudo-NMOS fine/coarse wired-or tapped delay line

Claim 1

A tapped delay line system (206) for delaying an input signal (203), comprising: (a) a plurality of fine delay elements (706, 708, 714) for receiving and delaying the input signal, each fine delay element having, (i) a data input; (ii) a data output; and (iii) a control input to receive a fine gate control time delay signal (306) for specifying a predetermined amount of delay for that fine delay element to add to the signal (203) applied to its respective data input; wherein said plurality of fine delay elements are coupled in series; (b) a plurality of coarse delay elements (716, 718, 726) for receiving the input signal from said plurality of fine delay elements and further delaying the input signal, each coarse delay element having, (i) a data input; (ii) a data output; and (iii) a control input to receive a coarse gate control time delay signal (306) for specifying a predetermined amount of delay for that coarse delay element to add to the signal (203) applied to its respective data input; wherein said plurality of coarse delay elements are coupled in series, and the data input of a first one of said plurality of coarse delay elements is coupled to the data output of a last one of said plurality of fine delay elements; and (c) a wired-OR multiplexer (215) having, (i) multiplexer data inputs (736 ... 746) connected to said data outputs of said plurality of coarse delay elements (716, 718...726) and the data output (734) of the last one of said plurality of fine delay elements (714); (ii) a select control input (748) to select one of said multiplexer data inputs to be output from said wired-OR multiplexer (215); (iii) a multiplexer output (204); and (iv) means (748) for passing said selected one of said multiplexer data inputs to said multiplexer output.

Claim 5

A method for delaying an input signal, comprising: (1) receiving the input signal into a plurality of fine delay elements (706, 708, 714) coupled in series, for delaying the input signal (203) thereby generating a finely delayed signal, each fine delay element having a data input, a data output and a control input; (2) receiving at said control inputs of said fine delay elements, a fine gate control time delay signal (306) for specifying a predetermined amount of delay for each fine delay element to add to the signal applied to its respective data input; (3) passing said finely delayed signal to a plurality of coarse delay elements (716, 718, 726) coupled in series, for further delaying said finely delayed signal, each coarse delay element having, a data input, a data output and a coarse delay element control input; (4) receiving at said coarse delay element control inputs, a coarse gate control time delay signal (306) for specifying a predetermined amount of delay for each coarse delay element to add to the signal applied to its respective data input, wherein the data input of a first one of said plurality of coarse delay elements (716) is coupled to the data output of a last one of said plurality of fine delay elements (714); and (5) selecting one of said data outputs (736, 738, 746) of said plurality of coarse delay elements or the data output (734) of the last one of said plurality of fine delay elements; and (6) outputting said selected data output.