EP0532316A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: JFE Steel Corp
•
Filing: 1992-09-10
•
Granted: —
•
Expires: 2012-09-10
Abstract
Abstract A semiconductor integrated circuit which has a CAM structure based on nonvolatile memories and is capable of effectively suppressing through current and utilizable for forming a flexible CAM of large scale integration comprises a first memory cell for defining the electrical connection or otherwise the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or otherwise the connection between a second data line and the match line, a selective transistor for making and breaking the connection between each of the first and the second data lines and the match line in accordance with the definition of the connections of the first and second memory cells. The semiconductor integrated circuit according to the present invention is capable of retrieving data from a number of memory cells at high speed without mutual interference and of providing an associative memory unit for use as a high-speed, large capacity data base.
Inventors
- 👤 Masato c/o Kawasaki Steel Corporation YONEDA
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:59
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/046
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
104 words
A semiconductor integrated circuit comprising a first memory cell for defining the electrical connection or otherwise the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or otherwise the connection between a second data line and said match line, and selective transistors for making and breaking the connection between each of said first and said second data lines and said match line in accordance with the definition of the connections of said first and second memory cells, wherein the threshold voltage of said selective transistor has a predetermined value incorporated during the fabrication process.
Claim 2
Dependent Claim
105 words
A semiconductor integrated circuit as claimed in claim 1, wherein a sense amplifier of a current driving type is connected to said match line and wherein a gate voltage Vw of said selective transistor satisfies the following conditions at the time of retrieval operation: V t ≦ V W ≦ V S + V t′ where V t : threshold voltage of the selective transistor (at the time of 0V substrate bias); V S : potential of a match line at the time of retrieval operation; V t′ : threshold voltage of the selective transistor subjected to substrate bias at the time of retrieval operation.
Claim 3
Dependent Claim
41 words
A semiconductor integrated circuit as claimed in either claim 1 or 2, wherein the voltage V t (at the time of 0V substrate bias) at the value incorporated in said selective transistor is set higher than that of any peripheral circuit.
Claim 4
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in anyone of claims 1 to 3, wherein said memory cells are composed of a nonvolatile memory element.
Claim 5
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 4, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.
Claim 6
Dependent Claim
67 words
A semiconductor integrated circuit as claimed in anyone of claims 1 to 5, wherein said circuit comprises a plurality of retrieval memory word blocks, said block including a set of said first and second memory cells, said selective transistors and a control word line for controlling said selective transistors, said match line and said sense amplifier are commonly used for said plurality of retrieval memory word blocks.
Claim 7
Dependent Claim
117 words
A semiconductor integrated circuit comprising a first memory cell for defining the electrical connection or otherwise the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or otherwise the connection between a second data line and said match line, a selective transistor for making and breaking the connection between each of said first and said second data lines and said match line in accordance with the definition of the connections of said first and second memory cells, means for electrically connecting a selective word line connected to the gate electrode of said selective transistor to said match line, and means for making said selective word line afloat.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 7, wherein the threshold voltage of said selective transistor has a predetermined value incorporated during the fabrication process.
Claim 9
Dependent Claim
95 words
A semiconductor integrated circuit as claimed in either claim 7 or 8, wherein a gate voltage V W of said selective transistor satisfies the following conditions at the time of retrieval operation: V t ≦ V W ≦ V H + V t′ where V t : threshold voltage of the selective transistor (at the time of 0V substrate bias); V H : H (high) potential of the data line at the time of retrieval operation; V t′ : threshold voltage of the selective transistor subjected to substrate bias at the time of retrieval operation.
Claim 10
Dependent Claim
45 words
A semiconductor integrated circuit as claimed in any one of the claims 7 to 9, wherein the threshold voltage V t (at the time of 0V substrate bias) at the value incorporated in said selective transistor is set higher than that of any peripheral circuit.
Claim 11
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in anyone of claims 7 to 10, wherein said memory cells are composed of a nonvolatile memory element.
Claim 12
Dependent Claim
20 words
A semiconductor integrated circuit as claimed in claim 11, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.
Claim 13
Dependent Claim
77 words
A semiconductor integrated circuit as claimed in anyone of claims 7 to 12, wherein said circuit comprises a plurality of retrieval memory word blocks, said block including a set of said first and second memory cells, said selective transistors and a control word line for controlling said selective transistors, said match line and a potential detecting means for detecting an electric potential of the match line are commonly used for said plurality of retrieval memory word blocks.
Claim 14
Dependent Claim
214 words
A semiconductor integrated circuit comprising a first nonvolatile memory cell for defining the electrical connection or otherwise the nonconnection between a first data line and a match line, a second nonvolatile memory cell for defining the electrical nonconnection or otherwise the connection between a second data line and said match line, and a control word line for controlling said first and second nonvolatile memory cells, said first and second nonvolatile cells and said control word line being combined into a retrieval memory word block, wherein the voltage of each signal line and the threshold voltage of each nonvolatile memory cell are so arranged as to satisfy the following equations (I) and (II) simultaneously at the time of data retrieval operation: V W - V H < V tL < V W - V L < V tH V W - V S < V tL where V tL : low threshold voltage of the nonvolatile memory cell; V tH : high threshold voltage of the nonvolatile memory cell; V H : H (high) potential of the data line at the time of retrieval operation; V L : L (low) potential of the data line at the time of retrieval operation; V S : potential of a match line at the time of retrieval operation.
Claim 15
Dependent Claim
30 words
A semiconductor integrated circuit as claimed in claim 14, wherein said nonvolatile memory cell is formed with a nonvolatile transistor having a threshold voltage satisfying said equations (I) and (II).
Claim 16
Dependent Claim
33 words
A semiconductor integrated circuit as claimed in claim 14, further comprising means for setting the voltage at the time of retrieval operation so that it can satisfy said equations (I) and (II) simultaneously.
Claim 17
Dependent Claim
34 words
A semiconductor integrated circuit as claimed in anyone of claims 14 to 16, wherein said nonvolatile memory element is at least one selected from the group consisting of mask ROM, EPROM, EEPROM and UVEPROM.
Claim 18
Dependent Claim
43 words
A semiconductor integrated circuit as claimed in anyone of claims 14 to 17, wherein said match line and a potential detecting means for detecting an electric potential of the match line are commonly used for a plurality of said retrieval memory word blocks.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.