Semiconductor memory cell and memory array with inversion layer

Claim 2

The memory cell (10) defined by claim 1, wherein said drain (14) is disposed within said substrate (12) and is formed by diffusion.

Claim 3

The memory cell (10) defined by claim 1, wherein said inversion source gate (18) is formed as part of a first layer of polysilicon, said floating gate (26) is formed as part of a second layer of polysilicon, said program gate (30) is formed as part of a third layer of polysilicon, and said access gate (34) is formed as part of a fourth layer of polysilicon.

Claim 4

The memory cell (10, 50) defined by claim 1, wherein a single electron injector structure material (28, 64) is disposed between said program gate (30, 66) and said floating gate (26, 62) where said program gate (30, 66) overlaps said floating gate (26, 62), said single electron injector structure material (28, 64) allowing electron flow from said floating gate (26, 62) to said program gate (30, 66).

Claim 5

The memory cell (10, 50) defined by claim 1, wherein a single electron injector structure material (24, 60) is disposed between said floating gate (26, 62) and said inversion source gate (18, 54) where said floating gate (26, 62) overlaps said inversion source gate (18, 54), said single electron injector structure material (24, 60) allowing electron flow from said inversion source gate (18, 54) to said floating gate (26, 62).

Claim 6

The memory cell (10, 50) defined by claim 1, wherein the capacitive coupling between said program gate (30, 66) and said floating gate (26, 62) is substantially greater than the capacitive coupling between said floating gate (26, 62) and said inversion source gate (18, 54).

Claim 7

The memory cell defined by claim 1, wherein the capacitive coupling between said program gate (30, 66) and said floating gate (26, 62) is greater than or equal to the capacitive coupling between said floating gate (26, 62) and the upper surface of said substrate (42, 52).

Claim 8

The memory cell (50) defined by claim 1, wherein said drain includes an inversion drain gate (56) disposed above the upper surface of said substrate (52), said inversion drain gate (56) inducing a depletion drain (ID) in said substrate (52) beneath said inversion drain gate (56) when a potential is applied thereto.

Claim 9

The memory cell (50) defined by claim 8, further comprising an isolation plate (57) aligned at least partially over said substrate (52) and configured to isolate said cell (50).

Claim 10

The memory cell (50) defined by claim 9, wherein said inversion source gate (54) and said inversion drain gate (56) are formed as part of a first layer of polysilicon, said isolation plate (57) is formed as part of a second layer of polysilicon, said floating gate (62) is formed as part of a third layer of polysilicon, said program gate (66) is formed as part of a fourth layer of polysilicon, and said access gate (70) is formed as part of a fifth layer of polysilicon.

Claim 11

The memory cell (50) defined by claim 9, wherein said substrate (52) comprises a P-type substrate and said isolation plate (57) is at ground potential.

Claim 12

The memory cell (50) defined by claim 9, wherein said floating gate (62) partially overlaps said isolation plate (57), and further comprising SEIS material (60) disposed between said floating gate (62) and said isolation plate (57) where said floating gate (62) overlaps said isolation plate (57), said SEIS material (60) allowing electron flow from said isolation plate (57) to said floating gate (62).

Claim 13

The memory cell (50) defined by claim 9, wherein said isolation plate (57) partially overlies each of said inversion drain gate (56) and said inversion source gate (54), and wherein said isolation plate (57) extends between said inversion drain gate (54) and said inversion source gate (56).

Claim 14

A memory cell (50) having five layers of polysilicon fabricated on a substrate (52), said memory cell (50) comprising: a first polysilicon gate layer comprising an inversion drain gate (56) and a separate inversion source gate (54), each of said inversion gates (54, 56) being disposed above said substrate (52) such that a depletion drain (ID) and a depletion source (IS) are respectively produced in said substrate (52) beneath said inversion drain gate (56) and said inversion source gate (54) when potentials are applied thereto, said depletion source (IS) and said depletion drain (ID) defining a channel region in said substrate (52); a second polysilicon gate layer comprising an isolation plate (57) for isolating said cell (50), said isolation plate (57) overlying a portion of said substrate (52) and said first polysilicon gate layer (54, 56); a third polysilicon gate layer comprising an electrically isolated floating gate (62), said third gate layer (62) being isolated from said substrate (52), said first gate layer (54, 56) and said second gate layer (57), said third gate layer (62) overlapping at least a portion of said second gate layer (57) and at least a portion of said substrate channel region; a fourth polysilicon gate layer comprising a program gate (66), said fourth gate layer (66) being isolated from said substrate (52), said first gate layer (54, 56), said second gate layer (57) and said third gate layer (62), said fourth polysilicon gate layer (66) overlapping at least a portion of said third gate layer (62); a fifth polysilicon gate layer comprising an access gate (70), said fifth gate layer (70) being isolated from said substrate (52), said first gate layer (54, 56), said second gate layer (57), said third gate layer (62) and said fourth gate layer (66), said fifth polysilicon gate layer (70) being aligned at least partially over said substrate channel region; and wherein application of a potential to said fourth gate layer (66) and simultaneous grounding of said second gate layer (57) establishes a cell write cycle in which said third gate layer (62) may be selectively charged positive or negative by respectively grounding or applying a potential to said inversion drain gate (56).

Claim 15

The memory cell (50) defined by claim 14, wherein said substrate (52) comprises a P-type substrate and said second gate layer (57) is at ground potential.

Claim 16

The memory cell (50) defined by claim 14, wherein the capacitive coupling between said fourth gate layer (66) and said third gate layer (62) is substantially greater than the capacitive coupling between said third gate layer (62) and said second gate layer (57).

Claim 17

The memory cell (50) defined by claim 14, wherein SEIS material (64) is disposed between said fourth gate layer (66) and said third gate layer (62) where said fourth gate layer (66) overlaps said third gate layer (62), said SEIS material (64) allowing electron flow from said third gate layer (62) to said fourth gate layer (66).

Claim 18

The memory cell (50) defined by claim 14, wherein SEIS material (60) is disposed between said third gate layer (62) and said second gate layer (57) where said third gate layer (62) overlaps said second gate layer (57), said SEIS material (60) allowing electron flow from said second gate layer (57) to said third gate layer (62).

Claim 19

A memory array fabricated on a substrate, said array comprising: a plurality of drain lines (D); a plurality of gate regions, each gate region being disposed above said substrate adjacent one of said plurality of drain lines (D), each of said plurality of gate regions including a floating gate (42, 74); a plurality of injection source gates, each injection source gate being disposed above said substrate (12, 52) adjacent at least one of said plurality of gate regions, each of said plurality of injection source gates inducing a depleted source line in said substrate (12, 52) upon application of a potential thereto, each depleted source line defining a channel region in said substrate (12, 52) extending to an associated one of said plurality of drain lines (D), each of said defined channel regions being at least partially disposed under the floating gate of the associated gate region; and wherein during a read cycle depleted source lines are established to pass charge through selected ones of said gate regions to their associated drain lines (D), and during a write cycle depleted source lines are removed to inject charge from selected injection source gates (40, 72) into the floating gates (42, 74) of the associated gate regions.

Claim 20

The memory array of claim 19, wherein each of said gate regions and associated drain line (D) and injection source gate comprises a memory cell (10, 50), and wherein each of said plurality of gate regions includes a program gate (40, 72), a plurality of said program gates (40, 72) being electrically connected to form a block of memory cells.

Claim 21

The memory array of claim 20, wherein said array is divided into an even number of memory cell (10, 50) blocks and wherein memory cells (10, 50) in two different blocks of said memory array share drain lines (D).

Claim 22

The memory array of claim 20, wherein said array is divided into an even number of memory cell (10, 50) blocks and wherein memory cells (10, 50) in two different blocks of said memory array share inversion source gates.

Claim 23

The memory array of claim 19, wherein each of said plurality of drain lines (D) includes an inversion drain gate (56) disposed above said substrate (52), each of said inversion drain gates (56) forming a depletion drain (ID) in said substrate with the application of a potential thereto.

Claim 24

A memory cell (10, 50) fabricated on a substrate (12, 52), said memory cell (10, 50) comprising: a drain line (D); a gate region (42, 74), said gate region being disposed above said substrate (12, 52) adjacent said drain line (D), said gate region including a floating gate (26, 62); an injection source gate (18, 54), said injection source gate (18, 54) being disposed above the substrate (12, 52) adjacent the gate region, said injection source gate (18, 52) inducing a depleted source line (IS) in said substrate (12, 52) upon application of a potential thereto, said depleted source line (IS) defining a channel region in said substrate extending to said drain line (D), said defined channel region being partially disposed under the floating gate (26, 62) of said gate region; and wherein during a read cycle a depleted source line (IS) is established to pass charge through said gate region to said drain line (D), and during a write cycle a depleted source line (IS) is removed to inject charge from the injection source gate (18, 54) into the floating gate (26, 62) of the gate region.

Claim 25

The memory cell (10, 50) of claim 24, wherein said drain line (D) includes an inversion drain gate (56) disposed above said substrate (52), said drain gate (56) forming a depletion drain (ID) in said substrate (52) with the application of a potential thereto.