EP0531100A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Baseband pulse shaper for GMSK modulators
Assignee: Advanced Micro Devices Inc
•
Filing: 1992-09-02
•
Granted: —
•
Expires: 2012-09-02
Abstract
Abstract A system provides and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data. The I baseband modulation signal is represented by I(t) = cos [2πf m ∫ g(t)dt] and the Q baseband modulation signal is represented by Q(t) = sin [2πf m ∫g(t)dt], wherein f m is the modulating frequency and g(t) is a filtered version of the serial bits of digital data. The system includes an input for receiving the serial bits of digital data, a memory including addressable memory locations for storing data representing the waveform amplitudes of the I and Q modulation baseband analog signals, and an address generator for addressing selected ones of the memory locations responsive to the serial bits of digital data. The system further includes digital to analog converters coupled to the memory for receiving the data stored at the memory locations addressed by the address generator and for converting the data to the I and Q modulation baseband analog signals.
Inventors
- 👤 Alfredo R. Linz
- 👤 Alan F. Hendrickson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:14
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2003; H04L27/2007; H04L27/2017; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03834; H04L25/03859
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
102 words
A system for producing a modulation baseband analog signal responsive to serial bits of digital data, said system comprising: input means for receiving said serial bits of digital data; memory means including addressable memory locations for storing data representing the waveform amplitudes of said modulation baseband analog signal; addressing means for addressing selected ones of said memory locations responsive to said serial bits of digital data; and digital to analog conversion means coupled to said memory means for receiving said data stored at said memory locations addressed by said addressing means and for converting said data to said modulation baseband analog signal.
Claim 2
Independent Claim
102 words
A system for producing a modulation baseband analog signal responsive to serial bits of digital data, said system comprising: input means for receiving said serial bits of digital data; memory means including addressable memory locations for storing data representing the waveform amplitudes of said modulation baseband analog signal; addressing means for addressing selected ones of said memory locations responsive to said serial bits of digital data; and digital to analog conversion means coupled to said memory means for receiving said data stored at said memory locations addressed by said addressing means and for converting said data to said modulation baseband analog signal.
Claim 3
Dependent Claim
50 words
A system as defined in claim 1 wherein said serial bits of digital data are received at said input means at a predetermined rate with each bit lasting a predetermined bit period and wherein said addressing means addresses said selected ones of said memory locations during each said bit period.
Claim 4
Dependent Claim
71 words
A system as defined in claim 2 wherein said modulation baseband analog signal is divisible into a finite number of waveform segments, each said waveform segment corresponding in length to one of said bit periods, wherein said data stored in said memory means includes data for each of said waveform segments, and wherein said addressing means addresses said memory locations for one of said waveform segments during each said bit period.
Claim 5
Dependent Claim
74 words
A system as defined in claim 3 wherein said memory means includes a plurality of memory portions, each said portion storing data representing a respective one of said waveform segments, and wherein said system further includes memory portion select means coupled to said addressing means for causing said addressing means to address the memory locations of one of said memory portions responsive to said serial bits of digital data during each said bit period.
Claim 6
Dependent Claim
27 words
A system as defined in claim 4 wherein said memory portion select means is responsive to the last three bits of said serial bits of digital data.
Claim 7
Dependent Claim
80 words
A system as defined in claim 5 wherein said input means includes a first delay means and a second delay means, said first and second delay means being coupled in series and arranged for delaying said serial bits of digital data by one said bit period, said first and second delay means also being coupled to said memory portion select means for providing said memory portion select means with said last three bits of said serial bits of digital data.
Claim 8
Dependent Claim
33 words
A system as defined in claim 4 further including control means for causing said addressing means to address said memory locations in ascending and descending order during alternating ones of said bit periods.
Claim 9
Dependent Claim
40 words
A system as defined in claim 4 further including control means coupled to said digital to analog conversion means for causing said digital to analog conversion means to sign inverse said waveform segments during selected one of said bit periods.
Claim 10
Dependent Claim
16 words
A system as defined in claim 1 wherein said memory means comprises a read only memory.
Claim 11
Dependent Claim
70 words
A system as defined in claim 1 further including ramp control means coupled to said input and to said addressing means, said ramp control means being responsive to the first one of said serial bits of digital data for causing said addressing means to address predetermined ones of said memory locations to cause the absolute magnitude of said modulation baseband analog signal to gradually increase from a value of zero.
Claim 12
Dependent Claim
58 words
A system as defined in claim 10 wherein said ramp control means is responsive to the last one of said serial bits of digital data for causing said addressing means to address said predetermined ones of said memory locations to cause the absolute magnitude of said modulation baseband analog signal to gradually decrease to a value of zero.
Claim 13
Independent Claim
168 words
A system for providing I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data, said I baseband modulation signal being represented by I(t) = cos [2 7 cf m fg(t)dt] and said Q baseband modulation signal being represented by Q(t) = sin [2 7 cf m fg(t)dt], wherein f m is the modulating frequency and g(t) is a filtered version of said serial bits of digital data, said system comprising: input means for receiving said serial bits of digital data; memory means including addressable memory locations for storing data representing the waveform amplitudes of said I and Q modulation baseband analog signals; addressing means for addressing selected ones of said memory locations responsive to said serial bits of digital data; and digital to analog conversion means coupled to said memory means for receiving said data stored at said memory locations addressed by said addressing means and for converting said data to said I and Q modulation baseband analog signals.
Claim 14
Independent Claim
168 words
A system for providing I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data, said I baseband modulation signal being represented by I(t) = cos [2 7 cf m fg(t)dt] and said Q baseband modulation signal being represented by Q(t) = sin [2 7 cf m fg(t)dt], wherein f m is the modulating frequency and g(t) is a filtered version of said serial bits of digital data, said system comprising: input means for receiving said serial bits of digital data; memory means including addressable memory locations for storing data representing the waveform amplitudes of said I and Q modulation baseband analog signals; addressing means for addressing selected ones of said memory locations responsive to said serial bits of digital data; and digital to analog conversion means coupled to said memory means for receiving said data stored at said memory locations addressed by said addressing means and for converting said data to said I and Q modulation baseband analog signals.
Claim 15
Independent Claim
85 words
A method of producing a modulation baseband analog signal responsive to serial bits of digital data, said method comprising the steps of: providing memory including addressable memory locations; storing data representing the waveform amplitudes of said modulation baseband analog signal in said memory; receiving said serial bits of digital data; addressing selected ones of said memory locations responsive to said serial bits of digital data; and converting said data stored at said addressed memory locations to analog form for providing said modulation baseband analog signal.
Claim 16
Independent Claim
85 words
A method of producing a modulation baseband analog signal responsive to serial bits of digital data, said method comprising the steps of: providing memory including addressable memory locations; storing data representing the waveform amplitudes of said modulation baseband analog signal in said memory; receiving said serial bits of digital data; addressing selected ones of said memory locations responsive to said serial bits of digital data; and converting said data stored at said addressed memory locations to analog form for providing said modulation baseband analog signal.
Claim 17
Independent Claim
149 words
A method for providing I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data, said I baseband modulation signal being represented by I(t) = cos [2pf m ∫ g(t)dt] and said Q baseband modulation signal being represented by Q(t) = sin [2πf m ∫ g(t)dt], wherein f m is the modulating frequency and g(t) is a filtered version of said serial bits of digital data, said method comprising the steps of: receiving said serial bits of digital data; providing memory including addressable memory locations; storing data representing the waveform amplitudes of said I and Q modulation baseband analog signals in said memory; addressing selected ones of said memory locations responsive to said serial bits of digital data; and converting said data stored at said addressed memory locations to analog form for providing said I and Q modulation baseband analog signals.
Claim 18
Independent Claim
149 words
A method for providing I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data, said I baseband modulation signal being represented by I(t) = cos [2pf m ∫ g(t)dt] and said Q baseband modulation signal being represented by Q(t) = sin [2πf m ∫ g(t)dt], wherein f m is the modulating frequency and g(t) is a filtered version of said serial bits of digital data, said method comprising the steps of: receiving said serial bits of digital data; providing memory including addressable memory locations; storing data representing the waveform amplitudes of said I and Q modulation baseband analog signals in said memory; addressing selected ones of said memory locations responsive to said serial bits of digital data; and converting said data stored at said addressed memory locations to analog form for providing said I and Q modulation baseband analog signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.