EP0530644A2
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EP
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Non-Volatile memory cell and fabrication method
Assignee: Texas Instruments Inc
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Filing: 1992-08-25
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Granted: —
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Expires: 2012-08-25
Abstract
Abstract In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.
Inventors
- 👤 Celtin Kaya
- 👤 David Liu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 17:26
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
77 words
A non-volatile memory cell structure comprising: heavily doped source and drain regions formed in the surface of a semiconductor substrate and separated by a channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region formed in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate.
Claim 2
Dependent Claim
26 words
The structure of claim 1 wherein said source and drain regions and said lightly doped region are n-doped silicon and said channel region is p-doped silicon.
Claim 3
Dependent Claim
15 words
The structure of claim 2 wherein said source and drain regions are doped with arsenic.
Claim 4
Dependent Claim
15 words
The structure of claim 2 wherein said source and drain regions are doped with phosphorus.
Claim 5
Dependent Claim
19 words
The structure of claim 1 wherein said lightly doped region is doped to between about 10¹³ and 10¹⁴ cm⁻².
Claim 6
Dependent Claim
16 words
The structure of claim 1 wherein said lightly doped region is doped with arsenic and/or phosphorous.
Claim 7
Dependent Claim
16 words
The structure of claim 1 wherein said cell is one cell is an array of cells.
Claim 8
Dependent Claim
34 words
The structure of claim 1 and further comprising a pocket region of conductivity type opposite that of said source and drain regions, said pocket region formed between said source region and said channel region.
Claim 9
Independent Claim
128 words
A method of forming a non-volatile memory device comprising the steps of: forming a gate stack on the surface of a semiconductor substrate, said gate stack comprising a floating gate insulatively overlying a channel region in said substrate and a control gate insulatively overlying said floating gate; forming a lightly doped region adjacent said gate stack, said lightly doped region spaced from the surface of said substrate and at least partially beneath said gate stack; forming a drain region on the side of the gate stack opposite said lightly doped region; forming sidewall insulators on said gate stack; and forming a main source region on the side of the gate stack of the first doped region such that said main source region does not underlie said gate stack.
Claim 10
Dependent Claim
18 words
The method of claim 9 wherein said floating gate and said control gate are formed by depositing polysilicon.
Claim 11
Dependent Claim
30 words
The method of claim 9 wherein said floating gate is insulated from said channel by an oxide and control gate is insulated from said floating gate by an oxide/nitride/oxide layer.
Claim 12
Dependent Claim
17 words
The method of claim 9 wherein said step of forming a lightly doped region comprises implanting impurities.
Claim 13
Dependent Claim
10 words
The method of claim 12 wherein said impurities comprise arsenic.
Claim 14
Dependent Claim
10 words
The method of claim 12 wherein said impurities comprise phosphorus.
Claim 15
Independent Claim
131 words
A method of forming a non-volatile memory device comprising the steps of: forming a gate stack on the surface of a semiconductor substrate, said gate stack comprising a floating gate insulatively overlying a channel region in said substrate and a control gate insulatively overlying said floating gate; forming first and second doped regions on opposite sides of said gate stack, said doped regions spaced from the surface of said substrate and at least partially beneath said gate stack; forming a drain region on the side of the gate stack of said second doped region; forming sidewall insulators on said gate stack; and forming a main source region on the side of the gate stack of the first doped region such that said main source region does not underlie said gate stack.
Claim 16
Dependent Claim
18 words
The method of claim 15 wherein said floating gate and said control gate are formed by depositing polysilicon.
Claim 17
Dependent Claim
30 words
The method of claim 15 wherein said floating gate is insulated from said channel by an oxide and control gate is insulated from said floating gate by an oxide/nitride/oxide layer.
Claim 18
Dependent Claim
17 words
The method of claim 15 wherein said step of forming a lightly doped region comprises implanting impurities.
Claim 19
Dependent Claim
10 words
The method of claim 18 wherein said impurities comprise arsenic.
Claim 20
Dependent Claim
18 words
The method of claim 19 wherein arsenic is implanted with an energy of about 100 to 200 keV.
Claim 21
Dependent Claim
10 words
The method of claim 18 wherein said impurities comprise phosphorus.
Claim 22
Dependent Claim
18 words
The method of claim 19 wherein arsenic is implanted with an energy of about 200 to 400 keV.
Claim 23
Dependent Claim
18 words
A non volatile memory device formed by a method as claimed in any of claims 9 to 22.
References Cited (Backward Citations)
No citation records indexed.
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