EP0529578A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semi-additive circuitry with raised features using formed mandrels
Assignee: Raytheon Co
•
Filing: 1992-08-25
•
Granted: —
•
Expires: 2012-08-25
Abstract
Abstract A circuit is produced by using a formed mandrel (10,12) and semi-additive techniques for creating circuit traces. A stainless steel mandrel (10) flash plated with copper (14) includes a depression (12) which will form a raised interconnection feature (24). Using a photolithographically formed pattern of photoresistive material (16) on the mandrel the selected pattern of circuit traces (18,20) and raised features (24) are electroplated onto the flash plated mandrel. After stripping the photoresist (16), a dielectric substrate is laminated to the circuit traces, effectively encapsulating the traces on three sides. After removing the laminated circuit traces and dielectric from the mandrel the flash plated copper (14) is removed and the circuit covered with an insulation coverlay. <IMAGE>
Inventors
- 👤 William R. Crumly
- 👤 Christopher M. Schreiber
- 👤 David B. Swarbrick
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:43
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; H; H05; H05K; H05K3/00; H05K3/10; H05K3/20; H05K3/205; H05K3/40; H05K3/4007; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0367; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10666; H05K2203/00; H05K2203/01; H05K2203/0104; H05K2203/0113; H05K2203/0147; H05K2203/0152; H05K2203/07; H05K2203/0703; H05K2203/0726; H05K2203/16; H05K2203/167; H05K3/36; H05K3/361; H05K3/365
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
104 words
Method of making a multi-layer circuit having raised features (24) comprising the steps of: forming a mandrel having at least one depression (12) therein, coating said mandrel and depression (12) with an electrically conductive material (14), additively forming a pattern of circuit traces (18, 20) on said coating (14) and in said depression (12), laminating a dielectric substrate (26) to said traces (18, 20) and depression (12), and removing said traces (18, 20) and substrate (26) and coating (14) from said mandrel, said step of additively forming comprising forming a raised feature (24) that projects from the plane of said circuit traces (18, 20).
Claim 2
Dependent Claim
51 words
Method according to claim 1, characterized in that said step of additively forming a pattern of circuit traces (18, 20) comprises the steps of applying a pattern of resist (16) to said coating (14), and electroforming conductive material (18) on said mandrel and coating (14) between elements of said resist pattern.
Claim 3
Dependent Claim
47 words
Method according to claim 1 or claim 2, characterized in that said step of coating said mandrel comprises flash plating, wherein said step of additively forming comprises electroplating, and including removing said coating (14) after said traces (18, 20) and substrate (26) are removed from said mandrel.
Claim 4
Dependent Claim
42 words
Method according to any of claims 1 - 3, characterized by the step of applying a stop coat to said pattern of circuit traces (18, 20) for protection of said circuit traces (18, 20) during said step of removing said coating (14).
Claim 5
Dependent Claim
69 words
Mandrel for forming a raised feature (24) multi-layer circuit by electrodeposition, comprising: a body (10) having a forming surface (11), a depression (12) in said surface (11) configured and arranged to form a raised feature (24) of a circuit to be formed on the mandrel, and an electrically conductive coating (14) on said forming surface (11) and depression (12), said coating (14) being readily separable from said surface (11).
Claim 6
Dependent Claim
18 words
Mandrel according to claim 5, characterized by a pattern of non-conductive material (16) formed on said coating (14).
Claim 7
Dependent Claim
77 words
Mandrel according to claim 5, characterized by a pattern of photoresist (16) on said coating (14), said photoresist (16) having a pattern that is the negative of a pattern of circuit traces (18, 20), whereby a pattern of circuit traces (18, 20) having a portion extending into said depression (12) may be electrodeposited on said coating (14) and laminated to a non-conductive substrate (26) by means of an adhesive which does not contact said forming surface (11).
Claim 8
Dependent Claim
122 words
Method for making a multi-layer electric circuit having raised features (24) comprising the steps of: forming a mandrel having a forming surface (11) and a raised mandrel feature (12), applying to said surface (11) and feature (12) an electrically conductive coating (14), additively forming a pattern of circuit traces (18, 20) on said coating (14), additively depositing a conductive material raised feature (24) on said mandrel feature (12), adhesively securing a substrate (26) to said circuit traces (18, 20) and conductive material raised feature (24), removing said substrate (26), circuit traces (18, 20), conductive material raised feature (24) and coating (14) from said mandrel, and removing said coating (14) from said traces (18, 20), conductive material raised feature (24) and substrate (26).
Claim 9
Dependent Claim
66 words
Method according to claim 8, characterized in that said mandrel includes a depression (12) shaped to form said conductive material raised feature (24), wherein said step of applying a coating (14) comprises applying the coating (14) to said depression (12), and wherein said step of forming a pattern of circuit traces (18, 20) comprises forming a part of said traces (18, 20) in said depression (12).
Claim 10
Dependent Claim
29 words
Method according to claim 8, characterized in that said step of forming a pattern of traces (18, 20) comprises electrodepositing a pattern of conductive material on said coating (14).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.