EP0529303A2
Expired / Lapsed
EP
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Checkpoint synchronization with instruction overlap enabled
Assignee: International Business Machines Corp
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Filing: 1992-07-21
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Granted: —
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Expires: 2012-07-21
Abstract
Abstract An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
Inventors
- 👤 Steven Tyler Comfort
- 👤 Clifford Owen Hayden
- 👤 John Stephen Liptay
- 👤 Susan Barbara Stillman
- 👤 Charles Franklin Webb
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
221 words
A method of enabling overlapped processing during execution of a checkpointing instruction in a processor having an architecture of a type wherein a first checkpoint is established before the instruction and a second checkpoint is established after the checkpointing instruction, comprising the steps of: decoding an instruction; determining whether the instruction is the checkpointing instruction; when it is determined that the instruction is the checkpointing instruction, blocking decoding of subsequent checkpointing instructions while continuing to enable decoding of other types of instructions; determining whether execution of the checkpoint instruction entails at least one operand store operation; when it is determined that the execution of the checkpoint instruction entails the at least one operand storage operation; identifying both a last operand store (store1) before the first checkpoint and a last operand store (store2) before the second checkpoint; generating a first checkpoint complete signal when store1 has been accomplished; generating a second checkpoint complete signal when store2 has been accomplished; when it is determined that the execution of the checkpoint instruction does not entail at least one operand storage operation, generating the first checkpoint complete signal and the second checkpoint complete signal; detecting when said first checkpoint signal and said second checkpoint signal have been generated; and, responsive to said detecting, completing the checkpointing instruction and re-enabling the decoding of subsequent checkpointing instructions.
Claim 2
Independent Claim
93 words
A method of enabling overlapped processing during execution of a checkpointing instruction, comprising the steps of: decoding an instruction; determining whether the instruction is the checkpointing instruction; when it is determined that the instruction is the checkpointing instruction, blocking decoding of subsequent checkpointing instructions while continuing to enable decoding of other types of instructions; determining whether all operand stores entailed by the checkpointing instruction have been accomplished; and, when it is determined that all of the operand stores have been accomplished, completing the checkpointing instruction and re-enabling the decoding of subsequent checkpointing instructions.
Claim 3
Dependent Claim
261 words
An apparatus for performing the method of claim 1, comprising: a decoder, said decoder comprising means for determining whether the instruction is the checkpointing instruction and for blocking decoding of subsequent checkpointing instructions responsive to said determining, said decoder further comprising means for continuing decoding of other types of instructions subsequent to said blocking; determining means, coupled to said decoder, for determining whether execution of the checkpoint instruction entails at least one operand store operation; marking means, coupled to said determining means, for identifying both a last operand store (store1) before the first checkpoint and a last operand store (store2) before the second checkpoint; signaling means, coupled to said marking means and said determining means, for generating a first checkpoint complete signal (UOC1) when store1 has been accomplished and for generating a second checkpoint complete signal (UOC2) when store2 has been accomplished; said signaling means further comprising means for generating both the UOC1 signal and UOC2 signal when it is determined that the execution of the checkpoint instruction does not entail at least one operand storage operation; detecting means, coupled to said signaling means, for detecting when said first checkpoint complete signal and said second checkpoint complete signal have been generated; execution means, coupled to said decoder, for executing said instructions; and, completion means, coupled to said execution means and said detecting means, for determining when said instructions are complete, said completion means comprising means for completing the checkpointing instruction and re-enabling the decoding of subsequent checkpointing instructions responsive to receipt of both of said UOC1 signal and said UOC2 signal.
Claim 4
Dependent Claim
123 words
An apparatus performing the method of claim 2, comprising means for decoding an instruction, said means for decoding comprising: means for determining whether the instruction is the checkpointing instruction and for blocking decoding of subsequent checkpointing instructions when it is determined that the instruction is the checkpointing instruction, said decoding means further comprising means for continuing to enable decoding of other types of instructions subsequent to said blocking; determining means, coupled to means for decoding, for determining whether all operand stores entailed by the checkpointing instruction have been accomplished; and, completion means, coupled to said determining means for completing the checkpointing instruction and re-enabling the decoding of subsequent checkpointing instructions when it is determined that all of the operand stores have been accomplished.
References Cited (Backward Citations)
No citation records indexed.
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