Method and circuit arrangement for movement detection in a television picture

Claim 2

Method according to claim 1, characterized in that the video signal sample has 8 bits.

Claim 3

Method according to claim 1 or 2, characterized in that the amplitude is cut into a 1-bit signal.

Claim 4

Method according to any previous claim, characterized in that the size of the blocks (BL) is 2 * 2 picture elements.

Claim 5

Method according to any previous claim, characterized in that the code word is formed according to the expression: where k is the length of the cut video signal sample, n is an integer, N is the number of picture elements (PIX) contained in the block (BL), and PIX n represents the picture elements (PIX) of the block (BL) and obtains as a value the value of the cut video signal samples.

Claim 6

Circuit arrangement to realize the method according to any previous claim, the arrangement comprising: a memory block (2) in which the picture is divided into blocks (BL) having the size of several picture elements (PIX) and containing at least one line memory (LT) and at least two delays (T); a comparison block (4) in which the code word generated for the block (BL) is compared with the code word of the corresponding block (BL) of the previous picture and containing a RAM memory (RAM)into which the previous picture is stored; and circuits (COMP) to perform the comparison, characterized in that it comprises: - a thresholding block (1), to which the video signal sample is supplied and where it is cut and from which it is supplied to the memory block (2), and - a coding block (3), to which the signal is supplied from the memory block (2) and where a code word is generated for the blocks (BL) using the video signal samples and which comprises shift-and-add circuits (SHIFT, ADD) and from which a signal is supplied to the comparison block (4).

Claim 7

A circuit arrangement according to claim 6, characterized in that the adding circuit of the coding block (3) has four inputs, and that - the first input receives from the thresholding block (1) via the line memory (LT) and the delay (T) the bit of the PIX₁ factor of the code word, - the second input receives from the thresholding block (1) via the line memory (LT) and the shift circuit (SHIFT) the bit of the PIX₂ factor of the code word, - the third input receives from the thresholding block (1) via the delay (T) and two shift circuits (SHIFT) the bit of the PIX₁ factor of the code word, and - the fourth input receives from the thresholding block (1) via the three shift circuits (SHIFT) the bit of the PIX₁ factor of the code word.

Claim 8

A circuit arrangement according to claim 6, characterized in that the RAM memory (RAM) of the comparison block (4) comprises a half field memory (720 * 288 * 4 bit).