EP0527010A2
Expired / Lapsed
EP
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Protection system for critical memory information
Assignee: Ascom Hasler Mailing Systems AG
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Filing: 1992-07-27
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Granted: —
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Expires: 2012-07-27
Abstract
Abstract A computer system, typically a postage meter system, has a processor (10), a memory (11, 12, 13), an address decoder (16), and a window circuit (70). The window circuit selectively couples the write strobe output (15) of the processor with the write strobe input of the memory in response to the processor's setting and clearing of a latched signal. A counter resets the processor if the latched signal is set and not cleared within a predetermined time period.
Inventors
- 👤 Tony Aebi
- 👤 Philippe Wicht
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 01:00
CPC Classifications
G; G07; G07B; G07B17/00; G07B17/00185; G07B17/00362; G07B2017/00395; G07B2017/00403
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
206 words
A computer system comprising: a processor (10) having a write strobe output (15) and address outputs operable to execute a stored program; a first memory (12) having a selection input and a write strobe input (72); address-decoding means (16) for providing a selection signal to the selection input of the first memory in response to associated address outputs from the processor; and window means (70), the window means comprising: first latch means (80) responsive to a first setting signal and a first clearing signal from the processor arranged to couple the write strobe output of the processor with the write strobe input of the first memory when the first latch means are set by the first setting signal, and for decoupling the write strobe output of the processor from the write strobe input of the first memory when the first latch means is cleared by the first clearing signal; and first counter means (83) responsive to the first setting signal and the first clearing signal from the processor for starting a counter upon receipt of the first setting signal, for clearing the counter upon receipt of the first clearing signal, and for interrupting the processor in the event of the counter reaching a first predetermined threshold.
Claim 2
Dependent Claim
206 words
A computer system comprising: a processor (10) having a write strobe output (15) and address outputs operable to execute a stored program; a first memory (12) having a selection input and a write strobe input (72); address-decoding means (16) for providing a selection signal to the selection input of the first memory in response to associated address outputs from the processor; and window means (70), the window means comprising: first latch means (80) responsive to a first setting signal and a first clearing signal from the processor arranged to couple the write strobe output of the processor with the write strobe input of the first memory when the first latch means are set by the first setting signal, and for decoupling the write strobe output of the processor from the write strobe input of the first memory when the first latch means is cleared by the first clearing signal; and first counter means (83) responsive to the first setting signal and the first clearing signal from the processor for starting a counter upon receipt of the first setting signal, for clearing the counter upon receipt of the first clearing signal, and for interrupting the processor in the event of the counter reaching a first predetermined threshold.
Claim 3
Dependent Claim
31 words
A computer system as claimed in claim 1, including a postage printer, and wherein the first memory is arranged to contain information indicative of an amount of postage available for printing.
Claim 4
Dependent Claim
43 words
A computer system as claimed in claim 1 or 2, wherein the first counter means further comprise means (83) responsive to receiving a command from the processor indicative of the first threshold value for setting the first predetermined threshold to the indicated value.
Claim 5
Dependent Claim
63 words
A computer system as claimed in claim 1, 2 or 3, wherein the first latch means are a first memory-mapped latch (80), the first setting signal comprises a processor write command of a first predetermined data value to the first memory-mapped latch, and the first clearing signal comprises a processor write command of a second predetermined data value to the first memory-mapped latch.
Claim 6
Dependent Claim
47 words
A computer system as claimed in claim 1, 2, 3 or 4, wherein the first counter means further comprise a second memory-mapped latch (84), and the command from the processor indicative of a threshold value comprises at least one processor write command to the second memory-mapped latch.
Claim 7
Dependent Claim
45 words
A computer system as claimed in any of claims 1 to 5, wherein the processor has a reset input (75) that resets the processor upon receipt of a reset signal, the first counter means being operable to interrupt the processor by generating the reset signal.
Claim 8
Dependent Claim
50 words
A computer system as claimed in any of claims 1 to 6, further comprising third latch means (74) responsive to receipt of the reset signal for storing information indicative of occurrence of the reset signal, the contents of the third latch means being available as an input to the processor.
Claim 9
Dependent Claim
197 words
A computer system as claimed in any of claims 1 to 7, further comprising a second memory (13) having a selection input and a write strobe input (73), the address-decoding means further providing a selection signal to the selection input of the second memory in response to associated address outputs from the processor, and the window means further comprising : second latch means (90) responsive to a second setting signal and a second clearing signal from the processor arranged to couple the write strobe output of the processor with the write strobe input of the second memory when the second latch means is set by the second setting signal, and for decoupling the write strobe output of the processor from the write strobe input of the second memory when the second latch means is cleared by the second clearing signal; and second counter means (93) responsive to the second setting signal and the second clearing signal from the processor for starting a counter upon receipt of the second setting signal, for clearing the counter upon receipt of the second clearing signal, and for interrupting the processor in the event of the counter reaching a second predetermined threshold.
Claim 10
Dependent Claim
40 words
A computer system as claimed in claim 8, wherein the second counter means further comprise means (93) responsive to receiving a command from the processor indicative of a threshold value for setting the second predetermined threshold to the indicated value.
Claim 11
Dependent Claim
62 words
A computer system as claimed in claim 8 or 9, wherein the second latch means are a third memory-mapped latch (90), the second setting signal comprises a processor write command of a third predetermined data value to the third memory-mapped latch, and the second clearing signal comprises a processor write command of a fourth predetermined data value to the third memory-mapped latch.
Claim 12
Dependent Claim
44 words
A computer system of claim 8, 9 or 10, wherein the second counter means further comprise a fourth memory-mapped latch (94), and the command from the processor indicative of a threshold value comprises at least one processor write command to the fourth memory-mapped latch.
Claim 13
Dependent Claim
28 words
A computer system as claimed in claim 8, 9, 10 or 11, wherein the second counter means are operable to interrupt the processor by generating the reset signal.
Claim 14
Dependent Claim
30 words
A computer system as claimed in any of claims 8 to 12, wherein the second predetermined threshold is set to an interval longer than that of the first predetermined threshold.
Claim 15
Dependent Claim
46 words
A computer system as claimed in claim 13, wherein the first memory is an EEPROM, the second memory is a battery-backed-up CMOS RAM, the first predetermined threshold is no greater than about 341 milliseconds, and the second predetermined threshold is no greater than about 682 milliseconds.
References Cited (Backward Citations)
No citation records indexed.
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