EP0526836A2
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EP
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QPSK demodulator with automatic frequency control
Assignee: Toshiba Corp
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Filing: 1992-07-29
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Granted: —
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Expires: 2012-07-29
Abstract
Abstract A QPSK modulated wave is inputted to an in- phase detector (2) and an orthogonal detector (3) which are supplied first and second frequency conversion carriers from a local oscillation unit (23). The detected components are converted to substantially a base band, and each component is digital-converted by A/D converters (6 and 7). Each digital component is spectrum-shaped by digital LPFs (8 and 9). The outputs of digital LPFs (8 and 9) are inputted to a complex multiplier (11) and calculated by use of first and second reproduction carriers and expressed as first and second calculation outputs, and inputted to a phase detector (12). The phase detector (12) obtains phase difference data between the phase expressed by the first and second calculation outputs and a predetermined phase and quadrant data of the phase. The phase difference data is used for a PLL. The PLL is formed by a filter (14), an NCO (15), data converters (16 and 17). The phase difference data is used for a AFC loop, and is inputted to a frequency error detection circuit (19) detecting a frequency error between the carrier frequency of the QPSK modulated wave and the oscillation frequency of the local oscillation unit (23). The frequency error output is smoothed by a filter (20) of an AFC loop, and used as a control signal controlling the oscillation frequency of the local oscillation unit (23). If the frequency error is large, the frequency error detection circuit (19) controls the AFC loop to be in an operation state and the PLL loop and the PLL loop to be in a fixed state. If the frequency error is small, the frequency error detection circuit (19) contains the control state of the AFC loop and switches the PLL loop to be the operation state.
Inventors
- 👤 Tatsuya C/O Intellectual Property Div. Ishikawa
- 👤 Noboru c/o Intellectual Property Div. Taga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 07:40
CPC Classifications
H; H03; H03M; H03M7/00; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2332; H04L27/0014; H04L2027/0024; H04L2027/0026; H04L2027/003; H04L2027/0032; H04L2027/0044; H04L2027/0053; H04L2027/0057; H04L2027/0071; H04L2027/0079; H04L2027/0081
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
323 words
A demodulator for demodulating a digitally modulated wave, characterized by comprising: a local oscillation unit (23) for oscillating first and second frequency converting carriers whose phase axes are different; a frequency converting unit (100) for converting components of first and second phase axes of a digital modulated wave to a frequency band, which is substantially a base band, by said first and second frequency converting carriers, wherein said components of first and second phase axes are digitally converted, each digital-converted component is spectrum-shaped by first and second digital low pass filters, thereby obtaining first and second digital signals; complex multiplier means (11) for multiplying said first and second digital signals by first and second reproducing carriers and for obtaining first and second calculation outputs having an expression of a complex number by a calculation of a complex number; means (12, 13) for obtaining phase difference data corresponding to a phase expressed by said first and second calculation outputs obtained by said complex multiplying means and quadrant data by a phase detection, and for obtaining a demodulation output having a multi-phase from said phase difference data and quadrant data; phase lock loop (PLL) means (14, 15, 16, 17) for outputting said first and second reproducing carriers by that a smoothing output by smoothing said phase difference data by a first loop filter, an oscillation frequency of a numerical value control oscillator is controlled by said smoothing output, and an oscillation output of said numerical value control oscillator is data-converted by a data converter; and AFC loop means (19, 20, 21) for controlling an oscillation frequency of said local oscillation unit by a smoothing output, wherein said phase difference data is inputted, a frequency error between the carrier frequency of said digital modulated wave and the oscillation frequency of said local oscillation unit is detected, thereby obtaining a frequency error output, and said smoothing output is obtained by smoothing the output of said frequency error.
Claim 2
Dependent Claim
323 words
A demodulator for demodulating a digitally modulated wave, characterized by comprising: a local oscillation unit (23) for oscillating first and second frequency converting carriers whose phase axes are different; a frequency converting unit (100) for converting components of first and second phase axes of a digital modulated wave to a frequency band, which is substantially a base band, by said first and second frequency converting carriers, wherein said components of first and second phase axes are digitally converted, each digital-converted component is spectrum-shaped by first and second digital low pass filters, thereby obtaining first and second digital signals; complex multiplier means (11) for multiplying said first and second digital signals by first and second reproducing carriers and for obtaining first and second calculation outputs having an expression of a complex number by a calculation of a complex number; means (12, 13) for obtaining phase difference data corresponding to a phase expressed by said first and second calculation outputs obtained by said complex multiplying means and quadrant data by a phase detection, and for obtaining a demodulation output having a multi-phase from said phase difference data and quadrant data; phase lock loop (PLL) means (14, 15, 16, 17) for outputting said first and second reproducing carriers by that a smoothing output by smoothing said phase difference data by a first loop filter, an oscillation frequency of a numerical value control oscillator is controlled by said smoothing output, and an oscillation output of said numerical value control oscillator is data-converted by a data converter; and AFC loop means (19, 20, 21) for controlling an oscillation frequency of said local oscillation unit by a smoothing output, wherein said phase difference data is inputted, a frequency error between the carrier frequency of said digital modulated wave and the oscillation frequency of said local oscillation unit is detected, thereby obtaining a frequency error output, and said smoothing output is obtained by smoothing the output of said frequency error.
Claim 3
Dependent Claim
100 words
The demodulator according to claim 1, characterized in that said AFC loop means (19, 20, 21) comprises: frequency error detection means (19) for obtaining a frequency error output by detecting a frequency error between the carrier frequency of said digital modulated wave and the oscillation frequency of said local oscillation unit; a second loop filter (20) smoothing said frequency error output sent from said frequency error detection means (19) and obtaining a smoothing output; and latch means (21) for latching the output of said second loop filter (20) to an oscillation frequency control terminal of said local oscillation unit (23).
Claim 4
Dependent Claim
105 words
The demodulator according to claim 2, characterized in that said frequency error detection means (19) comprises means for continuing the operation state of said AFC loop means (19, 20, 21) by setting the output of said latch means (21) to be in a through state and the output of said PLL loop means (14, 15, 16, 17) to be in a fixing state when said frequency error is large, and for controlling said PLL loop means (14, 15, 16, 17) to be in an operating state by maintaining the output of said latch means (21) when said frequency error is smaller than the predetermined value.
Claim 5
Dependent Claim
227 words
The demodulator according to claim 1, characterized in that said local oscillation unit (23) comprises: a numeral value control oscillator (22) supplying the output of said frequency error detection means (19, 20, 21); a data converter (24) data-converting the oscillation output of said numeral value control oscillator (22) by a sine conversion characteristic or a cosine conversion characteristic; a D/A converter (25) analog-converting the output of said data converter (24); a frequency gradually multiplying circuit (26 to 24) frequency-multiplying the output of said D/A converter (25); and a distributor (4) distributing the output of said frequency gradually multiplying circuit (26 to 24) to said first frequency converting carrier having a phase of 0 degree and said second frequency converting carrier having a phase of 90 degrees; and said frequency conversion unit (100) comprises: quasi-synchronous and orthogonal detection means (2, 3) for obtaining first and second detection outputs by carrying out multiplication of said first frequency converting carrier and said digital converted wave and multiplication of said second frequency converting carrier and said digital converted wave; first and second analog digital conversion means (6, 7) for digitally converting said first and second detection signals obtained by said quasi-synchronous and orthogonal detection means (2, 3); and first and second digital low pass filters (8, 9) spectrum-shaping the outputs of said first and second analog digital conversion means (6, 7).
Claim 6
Dependent Claim
225 words
The demodulator according to claim 1, characterized in that said local oscillation unit (23) comprises: first local oscillation circuits (4, 5) oscillating third and fourth frequency converting carriers whose phase axes are different by a fixed frequency; a numeral value control oscillator (22) supplying the output of said frequency error detection means; and a second local oscillation circuit having first and second data converters (31, 32) data-converting the oscillation output of said numeral value control oscillator (22) by a sine conversion characteristic and a cosine conversion characteristic; and said frequency conversion unit (100) comprises: quasi-synchronous and orthogonal detection means (2, 3) for obtaining first and second detection outputs by carrying out multiplication of said third frequency converting carrier and said digital converted wave and multiplication of said fourth frequency converting carrier and said digital converted wave; first and second analog-digital conversion means (6, 7) for digitally converting said first and second detection signals obtained by said quasi-synchronous and orthogonal detection means (2, 3); frequency converting means (33) for obtaining first and second frequency converting outputs having a complex expression by multiplying the outputs of said first and second analog-digital converting means (6, 7) by said first and second frequency converting carriers; and first and second digital low pass filters (8, 9) spectrum-shaping the outputs of said first and second analog digital conversion means (6, 7).
Claim 7
Dependent Claim
90 words
The demodulator according to claim 1, characterized in that said local oscillation unit (23) comprises: a data converter (24) data-converting the oscillation output of said numeral value control oscillator (22) by a sine conversion characteristic or a cosine conversion characteristic; a D/A converter (25) analog-converting the output of said data converter (24); a multiplier (401) multiplying the output of said D/A converter (25) by an oscillation output of a fixed frequency oscillator (402); and a band low pass filter (403) to which the output of said multiplier (401) is supplied.
Claim 8
Dependent Claim
134 words
The demodulator according to claim 1, characterized in that said local oscillation unit (23) comprises: a first data converter (24) data-converting the oscillation output of said numeral value control oscillator (22) by a sine conversion characteristic and a second data converter (25) data-converting said oscillation output by a cosine conversion characteristic; first and second D/A converters (25, 502) digital/analog-converting the outputs of said first and second data converters (24, 501), respectively; first and second multipliers (503, 504) multiplying the outputs of said first and second D/A converters (25, 502) by the oscillation outputs having a different phase sent from a fixed frequency oscillator (506); a synthesizer (507) synthesizing the outputs of said first and second multipliers (503, 504); and a band pass filter (508) to which the output of said synthesizer (507) is supplied.
References Cited (Backward Citations)
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