EP0526790A2
Expired / Lapsed
EP
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A folded bitline dynamic random access memory
Assignee: International Business Machines Corp
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Filing: 1992-07-18
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Granted: —
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Expires: 2012-07-18
Abstract
Abstract A folded bitline DRAM cell is described which includes a trench capacitor (102) and a planar-configured access transistor. The access transistor (112, 114) is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate (126, 128). A first wordline (136) has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal (140) is positioned adjacent the gate and a passing wordline (138) is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline (136). In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.
Inventors
- 👤 Sang H. Dhong
- 👤 Wei Hwang
- 👤 Lewis M. Terman
- 👤 Matthew R. Wordeman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 09:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/373
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
149 words
A folded bitline DRAM cell comprising: a substrate (100) having a major planar surface in which a plurality of trench capacitors (102) are embedded; an access transistor (112) stacked over at least one said capacitor and having at least first and second terminals (112, 116) configured parallel to said major planar surface, a first said terminal (122) connected to said trench capacitor (102); a gate (126, 128) for said transistor (112) positioned between said first and second terminals (122, 116) and oriented parallel to said major planar surface; a first wordline (136) having a minor surface in contact with said gate (126, 128) and a major surface orthogonally oriented with respect to said gate; an insulating pedestal (140) adjacent said gate; and a passing wordline (138) disposed on said pedestal (140), said passing wordline (138) having a major surface parallel to the major surface of said first wordline (136).
Claim 2
Dependent Claim
149 words
A folded bitline DRAM cell comprising: a substrate (100) having a major planar surface in which a plurality of trench capacitors (102) are embedded; an access transistor (112) stacked over at least one said capacitor and having at least first and second terminals (112, 116) configured parallel to said major planar surface, a first said terminal (122) connected to said trench capacitor (102); a gate (126, 128) for said transistor (112) positioned between said first and second terminals (122, 116) and oriented parallel to said major planar surface; a first wordline (136) having a minor surface in contact with said gate (126, 128) and a major surface orthogonally oriented with respect to said gate; an insulating pedestal (140) adjacent said gate; and a passing wordline (138) disposed on said pedestal (140), said passing wordline (138) having a major surface parallel to the major surface of said first wordline (136).
Claim 3
Dependent Claim
27 words
The folded bitline DRAM cell of claim 1 further comprising: an insulating mesa (142) disposed between said first and passing wordlines (136, 138) and in contact therewith.
Claim 4
Dependent Claim
52 words
The folded bitline DRAM cell of claim 1 or 2, further comprising: an insulating layer (144) disposed over said first and passing wordlines (136, 138) and insulating pedestal (142); and a bitline (120) disposed on said insulating layer (144) and in contact with said second terminal (116) of said access transistor (112).
Claim 5
Dependent Claim
61 words
The folded bitline DRAM cell of anyone of the claims 1 to 3 wherein each said trench capacitors (102) is provided with a concave recess filled with semiconductive material (110), said access transistor terminals (122, 116) formed in said semiconductive material (110) and said gate (126, 128) positioned over said semiconductive material (110) and separated therefrom by an insulating layer (130).
Claim 6
Dependent Claim
47 words
The folded bitline DRAM cell of claim 4, wherein a conductive material (106) forms a portion of a rim of said concave recess and serves as a contact for said trench capacitor (102), said first terminal (122) of said access transistor (112) making connection with said rim.
Claim 7
Dependent Claim
69 words
The folded bitline DRAM cell of claim 4 or 5 further comprising: an additional trench capacitor (102); an additional access transistor (114) stacked over said additional trench capacitor; and terminals of said additional transistor (114) formed in semiconductive material (110) which resides in a concave recess in said additional access trench capacitor (102), said additional access transistor sharing said second terminal (116) with said first recited access transistor (112).
Claim 8
Dependent Claim
107 words
The folded bitline DRAM cell of anyone of the claims 4 to 6 wherein said bitline (120) makes contact with said first terminal (116) of said access transistors (112, 114) via a stud (118) that is oriented orthogonally to said major planar surface, said stud (118) separating said access transistors (112, 114) and insulated therefrom, said additional access transistor (114) having a gate which makes contact with an additional wordline (136) that is, in turn, separated from an additional passing wordline (138) by an insulating mesa (142), said additional wordline and passing wordline oriented in a mirror image to said first above recited wordline and passing wordline.
Claim 9
Independent Claim
144 words
A method for fabricating a folded bitline DRAM cell on a semiconductor substrate in which a plurality of trench capacitors (102) have been formed, the method comprising the steps of: depositing a planar semiconductor region (110) that partially overlaps and spans a pair of adjacent trench capacitors (102); forming at least three contact areas (122, 116, 124) in said semiconductor region, at least a first two of said contact areas arrayed at extremities of said region and in contact with terminals of said adjacent trench capacitors (102); constructing a bitline stud (118) in contact with a third contact area (116); depositing a pair of gate structures (126, 128) between said third contact area (116) and said first and second contact areas, respectively; and producing wordlines (136) that contact said gate structures (126, 128), and passing wordlines (138) that are insulated from said gate structures.
Claim 10
Independent Claim
144 words
A method for fabricating a folded bitline DRAM cell on a semiconductor substrate in which a plurality of trench capacitors (102) have been formed, the method comprising the steps of: depositing a planar semiconductor region (110) that partially overlaps and spans a pair of adjacent trench capacitors (102); forming at least three contact areas (122, 116, 124) in said semiconductor region, at least a first two of said contact areas arrayed at extremities of said region and in contact with terminals of said adjacent trench capacitors (102); constructing a bitline stud (118) in contact with a third contact area (116); depositing a pair of gate structures (126, 128) between said third contact area (116) and said first and second contact areas, respectively; and producing wordlines (136) that contact said gate structures (126, 128), and passing wordlines (138) that are insulated from said gate structures.
Claim 11
Dependent Claim
118 words
The method as recited in claim 8 wherein said wordlines (136) and passing wordlines (138) are produced by the further steps of: depositing a first mesa (140) of insulating material adjacent each said gate structure (126, 128); depositing a second insulating mesa (142) at least partially on said first mesa (140), said second mesa overlapping a said gate structure (126, 128); applying a conformal coating of conductive material over said second mesa and in contact with said gate structure; and subsequently removing aspects of said conductive, material that are parallel to in the major plan and surface of said substrate to leave vertical strap portions (136, 138) thereof, said vertical strap portions acting as wordlines and passing wordlines.
Claim 12
Dependent Claim
45 words
The method as recited in claim 8 or 9 wherein said planar semiconductor region (110) is deposited in a recess in said adjacent trench capacitors (102), said first and second contact areas (112, 124) making electrical connection to rim portions of said trench capacitor terminals.
Claim 13
Dependent Claim
144 words
A folded bitline DRAM cells including a planar substrate (200) in which trench capacitors (202) have been embedded, the combination comprising: a semiconductor pedestal (212) adjacent a first edge of a said trench capacitor; an insulating pedestal (206) adjacent a second opposing edge of said trench capacitor; a first semiconductor terminal (210) formed on said semiconductor pedestal (212); a second semiconductor terminal (208) formed on an upper extent of a contact of said trench capacitor (202) and in communication with said semiconductor pedestal (212); and a first wordline (214) having major and minor surfaces, said major surface disposed between said first and second semiconductor terminals (210, 208) and juxtaposed to a side of said semiconductor pedestal (212), whereby said first wordline (216) forms a gate of an access transistor that includes said first and second semiconductor terminals (210, 208) as its source and drain.
Claim 14
Dependent Claim
144 words
A folded bitline DRAM cells including a planar substrate (200) in which trench capacitors (202) have been embedded, the combination comprising: a semiconductor pedestal (212) adjacent a first edge of a said trench capacitor; an insulating pedestal (206) adjacent a second opposing edge of said trench capacitor; a first semiconductor terminal (210) formed on said semiconductor pedestal (212); a second semiconductor terminal (208) formed on an upper extent of a contact of said trench capacitor (202) and in communication with said semiconductor pedestal (212); and a first wordline (214) having major and minor surfaces, said major surface disposed between said first and second semiconductor terminals (210, 208) and juxtaposed to a side of said semiconductor pedestal (212), whereby said first wordline (216) forms a gate of an access transistor that includes said first and second semiconductor terminals (210, 208) as its source and drain.
Claim 15
Dependent Claim
40 words
The folded bitline DRAM cells of claim 11, further comprising: a passing wordline (218) having major and minor surfaces, said major surface oriented parallel to the major surface of said first wordline (214)and in contact with a insulating pedestal (220).
Claim 16
Dependent Claim
36 words
The folded bitline DRAM cells of claim 11 or 12 wherein said first semiconductor terminal (210) is formed in a planar upper extent of said semiconductor pedestal (212) and makes contact with a bitline stud (226).
Claim 17
Dependent Claim
64 words
The folded bitline DRAM cells of anyone of the claims 11 to 13 wherein said trench capacitor comprises: a trench formed in said semiconductor substrate (200); a conductive material filling (204) said trench; and an insulating layer (206) positioned between said conductive material (204) and said semiconductor substrate (200), said insulating layer (206) exhibiting an increased thickness about an upper extent of said trench.
Claim 18
Dependent Claim
133 words
The folded bitline DRAM cells of anyone of the claims 11 to 14 wherein said semiconductor pedestal (212) is positioned between said first recited trench capacitor (202) and a first edge of second trench capacitor (202), the combination further comprising: a second insulating pedestal (220) adjacent a second opposing edge of said second trench capacitor; a third semiconductor terminal (208) formed on an upper extent of a contact to said second trench capacitor and in communication with said semiconductor pedestal (212); a second wordline (214) having major and minor surfaces, said major surface disposed between said first and third semiconductor terminals (210, 208) and juxtaposed to a side of said semiconductor pedestal (212) to thereby act as a gate of another access transistor that includes said first and third semiconductor terminals (210, 208).
Claim 19
Dependent Claim
42 words
The folded bitline DRAM cells as recited in claim 15 further comprising: a passing wordline (218) having major and minor surfaces, said major surface oriented parallel to the major surface of said first wordline and in contact with said insulating pedestal (220).
References Cited (Backward Citations)
No citation records indexed.
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