EP0526007A2
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EP
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Digitizer control circuit
Assignee: NCR International Inc
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Filing: 1992-07-03
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Granted: —
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Expires: 2012-07-03
Abstract
Abstract A digitizer control circuit (10) is disclosed which employs a tunable digitizer-screen energizing source (16,18,20). In addition, the digitizer control circuit includes a stylus (24) for sensing the energizing signal, and a circuit (30) for processing the information signal from the stylus (24), including a narrow bandpass filter (48) for passing the frequency of the energizing signal and minimizing the passage of extraneous noise. A controller (14) determines the location of the stylus (24) on the active surface of the energized digitizer screen (22) and controls operation of the circuit. The energized source includes a tunable divide-by-n circuit (16) employing an 8-bit latch (54), an 8-bit counter (56), and a state machine (58). A nonvolatile memory (34) stores the most recent value for the divisor value n.
Inventors
- 👤 Robert Llwellyn Protheroe
- 👤 Kazem Memarzadeh
- 👤 John Frederick Crooks
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:42
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/01; G06F3/03; G06F3/041; G06F3/044; G06F3/0441; G06F3/0442
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
95 words
Digitizer control apparatus comprising energizing means (16,18,20) arranged to produce an output signal for energizing a digitizer screen (22), sensing means (24) for sensing the energization of said screen (22) to produce a signal for indicating the position of said sensing means (24) on said screen (22), and processing means (30) for processing the signal produced by said sensing means (24), characterized in that the frequency of the output signal of said energizing means (16,18,20) is variable and is arranged to change in accordance with changes in a frequency characteristic of said processing means (30).
Claim 2
Dependent Claim
95 words
Digitizer control apparatus comprising energizing means (16,18,20) arranged to produce an output signal for energizing a digitizer screen (22), sensing means (24) for sensing the energization of said screen (22) to produce a signal for indicating the position of said sensing means (24) on said screen (22), and processing means (30) for processing the signal produced by said sensing means (24), characterized in that the frequency of the output signal of said energizing means (16,18,20) is variable and is arranged to change in accordance with changes in a frequency characteristic of said processing means (30).
Claim 3
Dependent Claim
31 words
Apparatus according to claim 1, characterized by means (26) for grounding said sensing means (24) to allow controlling means (14) to measure any direct voltage bias in said processing means (30).
Claim 4
Dependent Claim
17 words
Apparatus according to claim 2, characterized in that said energizing means (16,18,20) comprises a variable frequency generator.
Claim 5
Dependent Claim
39 words
Apparatus according to claim 2, characterized in that said energizing means (16,18,20) comprises a tunable divide-by-n circuit and a clock (12) coupled to the tunable divide-by-n circuit through said controlling means (14) for driving the tunable divide-by-n circuit (16).
Claim 6
Dependent Claim
125 words
Apparatus according to claim 4, characterized in that said tunable divide-by-n counter (16) comprises an 8-bit latch (54) coupled to said controlling means (14) for storing an 8-bit register value related to the divisor value n, an 8- bit counter (56) coupled to the seven most significant bits of said 8-bit latch (54) and to the clock output of said controlling means (14), for producing a first quotient output, and a state machine (58) coupled to the least significant bit of said 8-bit latch (54), the first quotient output of said 8-bit counter (56) and the clock output of said controlling means (14), for producing a second quotient output related to the energizing signal and for producing an output for reloading said 8-bit counter (56).
Claim 7
Dependent Claim
56 words
Apparatus according to claim 4 or 5, characterized in that said energizing means includes a bandpass filter (18) coupled to the output of said tunable divide-by-n counter (16) and means (20), coupled to the output of said bandpass filter (18) and controlled by said controlling means (14), for selectively applying the energizing signal to said digitizer.
Claim 8
Dependent Claim
40 words
Apparatus according to claim 6, characterized by switch means (29), controlled by said controlling means (14), for coupling the output of said bandpass filter (18) to the output of said sensing means (24) during tuning of the tunable divide-by-n counter.
Claim 9
Dependent Claim
57 words
Apparatus according to any one of the preceding claims, characterized in that said processing means (30) comprises a preamplifier (28) coupled between said sensing means (24) and filtering means (48), an AC-to-DC converter (50) coupled to the output of said filtering means (48), and an analog-to-digitial converter (32) coupled to the output of said AC-to-DC converter (50).
Claim 10
Dependent Claim
25 words
Apparatus according to claim 7, characterized by non-volatile memory means (34) coupled to said controlling means (14), for storing the most recent value of n.
Claim 11
Dependent Claim
94 words
A tunable divide-by-n circuit (16) characterized by an 8-bit latch (54) for storing an 8-bit register value related to the divisor value n, an 8-bit counter (56) coupled to the seven most significant bits of said 8-bit latch (54) and to a clock (68) for producing a first quotient output, and a state machine (58) coupled to the least significant bit of said 8-bit latch (54), the first quotient output of said 8-bit counter (56) and said clock (68), for producing a second quotient output and an output for reloading said 8-bit counter (56).
Claim 12
Dependent Claim
94 words
A tunable divide-by-n circuit (16) characterized by an 8-bit latch (54) for storing an 8-bit register value related to the divisor value n, an 8-bit counter (56) coupled to the seven most significant bits of said 8-bit latch (54) and to a clock (68) for producing a first quotient output, and a state machine (58) coupled to the least significant bit of said 8-bit latch (54), the first quotient output of said 8-bit counter (56) and said clock (68), for producing a second quotient output and an output for reloading said 8-bit counter (56).
References Cited (Backward Citations)
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