Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
102 words
A data processing device comprising a data processing circuit for processing a device input signal into a processed output signal, a sequential circuit for processing a processed input signal into a device output signal, and supply means for supplying said processed output signal to said sequential circuit as said processed input signal, said device input signal being obtained by multiplexing input data signals of a plurality of channels, wherein said sequential circuit comprises multiport random access memory means for memorizing said processed input signal as memorized signals according to said channels and for producing said memorized signals as said device output signal.
Claim 2
Dependent Claim
102 words
A data processing device comprising a data processing circuit for processing a device input signal into a processed output signal, a sequential circuit for processing a processed input signal into a device output signal, and supply means for supplying said processed output signal to said sequential circuit as said processed input signal, said device input signal being obtained by multiplexing input data signals of a plurality of channels, wherein said sequential circuit comprises multiport random access memory means for memorizing said processed input signal as memorized signals according to said channels and for producing said memorized signals as said device output signal.
Claim 3
Dependent Claim
93 words
A data processing device as claimed in Claim 1, said channels being P in number, wherein said multiport random access memory means comprises: a write and read clock counter for producing an M-bit write and read address signal, where M represents an integer which is not less than one and is less than (log 2 P + 1); and a multiport random access memory supplied with said processed input signal and said write and read address signal for memorizing said memorized signals and for producing said memorized signals as said device output signal.
Claim 4
Dependent Claim
168 words
A data processing device as claimed in Claim 2, said write and read clock counter being a first M-bit clock counter for producing said write and read address signal as a first address signal to make said multiport random access memory produce said device output signal as a first device output signal, wherein: said multiport random access memory means further comprises second through N-th M-bit clock counters for producing second through N-th address signals, where N represents an integer which is not less than one; said data processing device comprising additional supply means for supplying said first device output signal to said data processing circuit as a circuit input signal to make said data processing circuit process said circuit input signal into said processed output signal; said multiport random access memory being supplied with said second through and N-th address signals in addition to said first address signal to produce said memorized signals as second through N-th device output signals in addition to said first device output signal.
Claim 5
Dependent Claim
57 words
A data processing device as claimed in Claim 1, 2 or 3, said data processing device being supplied additionally with a test signal, wherein said supply means is controlled by a data/test selection signal to supply said processed output signal and said test signal selectively as said processed input signal to said multiport random access memory means.
Claim 6
Dependent Claim
41 words
A data processing device as claimed in Claim 4, wherein said multiport random access memory means is for producing said device output signal as a sequential circuit test output signal when supplied with said test signal as said processed input signal.
Claim 7
Dependent Claim
98 words
A data processing device as claimed in Claim 5, further comprising an additional supply means for supplying said sequential circuit test output signal to said data processing circuit as a circuit input signal, wherein: said data processing circuit processes said circuit input signal into an additional processed output signal; the first-mentioned supply means supplying said additional processed output signal to said multiport random access memory means as an additional processed input signal; said multiport random access memory means producing said device output signal as a processing circuit test output signal when supplied with said additional processed input signal.